Freescale Semiconductor MPC860T MII Async Inputs Signal Timing CRS, COL, Txen Txer, Crs, Col

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

M7

TX_CLK (input)

M5

M8

TXD[3:0] (outputs)

TX_EN

TX_ER

M6

Figure 7-2. MII Transmit Signal Timing Diagram

7.3.3 MII Async Inputs Signal Timing (CRS, COL)

Table 7-3 provides information on the MII async inputs signal timing, shown in Figure 7-3.

Table 7-3. MII Async Inputs Signal Timing

Num	Characteristic	Min	Max	Unit
M9	CRS, COL minimum pulse width	1.5	Ñ	TX_CLK period

Figure 7-3 shows the MII asynchronous inputs signal timing diagram.

CRS, COL

M9

Figure 7-3. MII Async Inputs Timing Diagram

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