Main
Page
Overview
Fast Ethernet Controller Operation
FEC External Signals
Parallel I/O Ports
Programming Model
SDMA Bus Arbitration and Transfers
Electrical Characteristics
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Page
ILLUSTRATIONS
TABLES
TABLES
Chapter 1 Overview
1.2 Overview
1.1 Document Revision History
1.3 Comparison with the MPC860
1.4 Features
1.4.1 MPC860TBlock Diagram
1-4
1.4.2 SIU Interrupt Conguration
1.5 Glueless System Design
Figure 1-3. MPC860T Serial Configuration
2-1
Chapter 2. FEC External Signals
Chapter 2 FEC External Signals
Table 2-1. FEC Signal Descriptions
2.1 Signal Descriptions
Table 2-1. FEC Signal Descriptions (Continued)
2-3
Chapter 2. FEC External Signals
Table 2-1. FEC Signal Descriptions (Continued)
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3-1
Chapter 3. Fast Ethernet Controller Operation
Chapter 3 Fast Ethernet Controller Operation
This chapter discusses the operation of the FEC.
3.1 Transceiver Connection
Serial-mode connections to the external transceiver are shown in Table 3-2.
3.2 FEC Frame Transmission
3.3 FEC Frame Reception
3.4 CAM Interface
3.5 FEC Command Set
3.6 Ethernet Address Recognition
3.7 Hash Table Algorithm
3.8 Inter-Packet Gap Time
3.9 Collision Handling
3.10 Internal and External Loopback
3.11 Ethernet Error-Handling Procedure
3.11.1 Transmission Errors
3.11.2 Reception Errors
3-8 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
Table 3-4. Reception Errors
Chapter 4 Parallel I/O Ports
4.1 Port D Pin Functions
4-2 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
Table 4-1 shows the port D pin assignments.
4.1.1 Port D Registers
Port D has three memory-mapped, read/write, 16-bit control registers.
4.1.2 Enabling MII Mode
To enable MII mode, do the following: 1. Write 0x1FFF to PDPAR. 2. Write 0x1FFF to PDDIR.
Table 4-1. Port D Pin Assignment
Chapter 5 SDMA Bus Arbitration and Transfers
5.1 Overview
5.2 The SDMA Registers
5-2 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
5.2.1 SDMA Conguration Register (SDCR)
Table 5-1 describes SDCR elds.
Figure 5-2. SDMA Configuration Register (SDCR) Table 5-1. SDCR Field Descriptions
Chapter 6 Programming Model
6.1 Overview
6.2 Parameter RAM
6-2 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
6.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)
Figure 6-1. ADDR_LOW Register
Table 6-1. FEC Parameter RAM Memory Map (Continued)
6.2.2 RAM Perfect Match Address High (ADDR_HIGH)
6.2.3 RAM Hash Table High (HASH_TABLE_HIGH)
6-4 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
Table 6-4 describes HASH_TABLE_HIGH elds.
6.2.4 RAM Hash Table Low (HASH_TABLE_LOW)
Figure 6-4. HASH_TABLE_LOW Register
Figure 6-3. HASH_TABLE_HIGH Register Table 6-4. HASH_TABLE_HIGH Field Descriptions
6.2.5 Beginning of RxBD Ring (R_DES_START)
6.2.6 Beginning of TxBD Ring (X_DES_START)
6.2.7 Receive Buffer Size Register (R_BUFF_SIZE)
MOTOROLA Chapter 6. Programming Model 6-7
Table 6-8 describes R_BUFF_SIZE elds.
6.2.8 Ethernet Control Register (ECNTRL)
Figure 6-7. R_BUFF_SIZE Register Table 6-8. R_BUFF_SIZE Field Descriptions
Figure 6-8. ECNTRL Register
6.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK)
MOTOROLA Chapter 6. Programming Model 6-9
and RFINT to notify at the end of frame.
6.2.10 Ethernet Interrupt Vector Register (IVEC)
Table 6-10. I_EVENT/I_MASK Field Descriptions
6.2.11 RxBD Active Register (R_DES_ACTIVE)
6.2.12 TxBD Active Register (X_DES_ACTIVE)
6.2.13 MII Management Frame Register (MII_DATA)
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6.2.14 MII Speed Control Register (MII_SPEED)
6.2.15 FIFO Receive Bound Register (R_BOUND)
6.2.16 FIFO Receive Start Register (R_FSTART)
6.2.17 Transmit Watermark Register (X_WMRK
6.2.18 FIFO Transmit Start Register (X_FSTART)
6-18 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
Table 6-20 describes X_FSTART elds.
6.2.19 DMA Function Code Register (FUN_CODE)
Figure 6-19. FUN_CODE Register
Figure 6-18. X_FSTART Register Table 6-20. X_FSTART Field Descriptions
MOTOROLA Chapter 6. Programming Model 6-19
Table 6-21 describes FUN_CODE elds.
6.2.20 Receive Control Register (R_CNTRL)
Table 6-21. FUN_CODE Field Descriptions
Figure 6-20. R_CNTRL Register
6-20 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
Table 6-22 describes R_CNTRL elds.
6.2.21 Receive Hash Register (R_HASH)
Figure 6-21. R_HASH Register
Table 6-22. R_CNTRL Field Descriptions
MOTOROLA Chapter 6. Programming Model 6-21
Table 6-22 describes R_HASH elds.
6.2.22 Transmit Control Register (X_CNTRL)
Table 6-24 describes X_CNTRL elds.
Table 6-23. R_HASH Field Descriptions
Figure 6-22. X_CNTRL Register Table 6-24. X_CNTRL Field Descriptions
6.3 Initialization Sequence
6.3.1 Hardware Initialization
6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN])
6.3.2.1 Descriptor Controller Initialization
6.3.2.2 User Initialization (after Asserting ECNTRL[ETHER_EN])
6.4 Buffer Descriptors (BDs)
6.4.1 Ethernet Receive Buffer Descriptor (RxBD)
The RxBD format is shown in Table 6-27.
MOTOROLA Chapter 6. Programming Model 6-25
6.4.2 Ethernet Transmit Buffer Descriptor (TxBD)
MOTOROLA Chapter 6. Programming Model 6-27
Table 6-29. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued)
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Chapter 7 Electrical Characteristics
7.1 DC Electrical Characteristics
7.2 AC Electrical Characteristics
7.3 Electrical Specications
7.3.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, RX_CLK)
7.3.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
MOTOROLA Chapter 7. Electrical Characteristics 7-3
Figure 7-2. MII Transmit Signal Timing Diagram
7.3.3 MII Async Inputs Signal Timing (CRS, COL)
Figure 7-3. MII Async Inputs Timing Diagram
Table 7-3. MII Async Inputs Signal Timing
7-4 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
7.3.4 MII Serial Management Channel Timing (MDIO,MDC)
Figure 7-4 shows the MII serial management channel timing diagram.
Figure 7-4. MII Serial Management Channel Timing Diagram
Table 7-4. MII Serial Management Channel Timing
MOTOROLA Chapter 7. Electrical Characteristics 7-5
7.4 MPC860T Pin Assignments
Figure 7-5 shows the MPC860T pin assignments. Pins that support the FEC are shown in black.
Figure 7-5. MPC860T Pinout DiagramTop View
