Hash Table Algorithm | Freescale Semiconductor MPC860T manual

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Freescale Semiconductor, Inc.

broadcast address. If it is, the frame is accepted unconditionally; otherwise (multicast address) a hash table lookup is performed using the 64-entry hash table deÞned in the hash table registers.

In promiscuous mode (R_CNTRL[PROM] = 1), the FEC receives all the incoming frames regardless of their address. In this mode the DA lookup is still performed and the MISS bit in the RxBD is set accordingly. If address recognition did not achieve a match, the frame is received with RxBD[MISS] set. If address recognition achieves a match the frame is received without the MISS bit being set.

	Check Address
	I/G Address	I
	I/G Address
	?
	G
True	Broadcast
	Address
	?
Receive Frame	False
True	Hash Match
	Hash Match
	?
Receive Frame	False

			False		Perfect Match		True
					?

								Receive Frame

Promiscuous				True (R_CNTRL[PROM] = 1)
Mode
?
?
	False						Receive Frame
	(R_CNTRL[PROM] = 1)						Receive Frame
	(R_CNTRL[PROM] = 1)							Set Miss Bit
								Set Miss Bit

Discard Frame

Figure 3-1. Ethernet Address Recognition Flowchart

3.7 Hash Table Algorithm

This section discusses the hash table process used in group hash Þltering. When the FEC receives a frame with the destination address I/G bit set, the 48-bit address is mapped into one of 64 bins, represented by the 64 bits in the two hash table registers. This is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting 6 bits

MOTOROLAChapter 3. Fast Ethernet Controller Operation3-5

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Freescale Semiconductor MPC860T user manual Hash Table Algorithm, Rcntrlprom =

Contents

Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet Controller Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number Illustrations Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision History Comparison with the MPC860 Features 1 MPC860TBlock Diagram System Interface Unit SIU Embedded PowerPC Processor CoreFast Ethernet Controller SIU Interrupt ConÞguration Glueless System Design Inc FEC Signal Descriptions Signal DescriptionsName Pin Description Miimdc L1RSYNCBRXD3 Miitxer MIITXD2 REJECT3REJECT4 MIITXD1 Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FEC FEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0 FEC Frame Reception CAM Interface FEC Command SetEthernet Address Recognition Rcntrlprom = Hash Table Algorithm Collision Handling Inter-Packet Gap Time Transmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External Loopback Reception Errors Port D Pin Functions Chapter Parallel I/O Ports Signal Function Enabling MII ModePort D Registers Shows the port D pin assignments CLK Sdma Registers Sdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID Bits Brießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description Section RAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh Þelds Describes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions Hashhigh Beginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart Þelds Describes Xdesstart Þelds Receive Buffer Size Register RbuffsizeXdesstart Field Descriptions Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field Descriptions Describes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions Fecpinmux Rfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr 11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions Ilevel 12 describes Rdesactive Þelds TxBD Active Register Xdesactive12. Rdesactive Field Descriptions 13 describes Xdesactive Þelds MII Management Frame Register Miidata13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds 15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed 17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field Descriptions Transmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field Descriptions 19 bit Þeld descriptions for Xwmrk Fifo Transmit Start Register Xfstart19. Xwmrk Field Descriptions 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 21 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo 22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej 22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field Descriptions Initialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware Initialization Descriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step Description Buffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step 27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO1 29 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSL Data Xcntrlhbc = Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcations MII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max Unit MII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COL MII Serial Management Channel Timing Shows the MII serial management channel timing diagram MPC860T Pin Assignments Following pins are marked as spare on Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product