Freescale Semiconductor MPC860T user manual Comparison with the MPC860, Features

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

The MPC860T integrates three separate processing blocks. The Þrst two, common with all MPC860 devices, are as follows:

¥A high-performance PowerPCª core that can be used as a general purpose processor for application programming

¥A RISC engine embedded in the communications processor module (CPM) designed to provide the communications protocol processing provided by the MPC860MH.

¥A 10/100 Fast Ethernet controller with integrated FIFOs and bursting DMA. Because the FEC block is implemented independently, the MPC860T provides high-performance Fast Ethernet connectivity without affecting the performance of the CPM. All of the performance and functionality of the MPC860MH is fully supported, including Ethernet.

Additionally, as the CPM of the MPC860T is based on the CPM of the MPC860MH, support for the QMC protocol is also provided. This enables the MPC860T to provide protocol processing (HDLC or transparent mode) for 64 time-division multiplexed channels at 50 MHz. This support for multichannel protocol processing and 10/100 Ethernet in one chip makes the MPC860T ideal for products such as high-performance, low-cost remote access routers.

Note that for existing parts, adding FEC functionality affects port D signal multiplexing.

1.3 Comparison with the MPC860

The MPC860T is pin compatible with the MPC860, so it may be used in similar applications with minimal modiÞcation. The electrical characteristics and mechanical data are nearly identical, with the exception of port D and the four no connect pins on the MPC860, which make up the media independent interface (MII). Most of the MII pins are multiplexed with the port D pins.

1.4 Features

The following sections summarize key FEC features.

¥10/100 base-T support

ÑFull compliance with the IEEE 802.3u standard for 10/100 base-T

ÑSupport for three different physical interfaces: 100-Mbps 802.3 media-independent interface (MII), 10-Mbps 802.3 MII, and 10-Mbps 7-wire interface

ÑLarge on-chip transmit and receive FIFOs to support a variety of bus latencies

ÑRetransmission from the transmit FIFO after a collision

ÑAutomatic internal ßushing of the receive FIFO for runts and collisions

ÑExternal BD tables of user-deÞnable size allow nearly unlimited ßexibility in

1-2MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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