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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
The MPC860T integrates three separate processing blocks. The Þrst two, common with all MPC860 devices, are as follows:
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¥A RISC engine embedded in the communications processor module (CPM) designed to provide the communications protocol processing provided by the MPC860MH.
¥A 10/100 Fast Ethernet controller with integrated FIFOs and bursting DMA. Because the FEC block is implemented independently, the MPC860T provides
Additionally, as the CPM of the MPC860T is based on the CPM of the MPC860MH, support for the QMC protocol is also provided. This enables the MPC860T to provide protocol processing (HDLC or transparent mode) for 64
Note that for existing parts, adding FEC functionality affects port D signal multiplexing.
1.3 Comparison with the MPC860
The MPC860T is pin compatible with the MPC860, so it may be used in similar applications with minimal modiÞcation. The electrical characteristics and mechanical data are nearly identical, with the exception of port D and the four no connect pins on the MPC860, which make up the media independent interface (MII). Most of the MII pins are multiplexed with the port D pins.
1.4 Features
The following sections summarize key FEC features.
¥10/100
ÑFull compliance with the IEEE 802.3u standard for 10/100
ÑSupport for three different physical interfaces:
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ÑRetransmission from the transmit FIFO after a collision
ÑAutomatic internal ßushing of the receive FIFO for runts and collisions
ÑExternal BD tables of
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