Freescale Semiconductor MPC860T user manual Parallel I/O Ports

Freescale Semiconductor, Inc...

	Freescale Semiconductor, Inc.
	CONTENTS
Paragraph	Title	Page
Number		Number
	Chapter 4
	Parallel I/O Ports
4.1	Port D Pin Functions	4-1
4.1.1	Port D Registers	4-2
4.1.2	Enabling MII Mode	4-2
	Chapter 5
	SDMA Bus Arbitration and Transfers
5.1	Overview	5-1
5.2	The SDMA Registers	5-1
5.2.1	SDMA Configuration Register (SDCR)	5-2
	Chapter 6
	Programming Model
6.1	Overview	6-1
6.2	Parameter RAM	6-1
6.2.1	RAM Perfect Match Address Low Register (ADDR_LOW)	6-2
6.2.2	RAM Perfect Match Address High (ADDR_HIGH)	6-3
6.2.3	RAM Hash Table High (HASH_TABLE_HIGH)	6-3
6.2.4	RAM Hash Table Low (HASH_TABLE_LOW)	6-4
6.2.5	Beginning of RxBD Ring (R_DES_START)	6-5
6.2.6	Beginning of TxBD Ring (X_DES_START)	6-5
6.2.7	Receive Buffer Size Register (R_BUFF_SIZE)	6-6
6.2.8	Ethernet Control Register (ECNTRL)	6-7
6.2.9	Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK)	6-8
6.2.10	Ethernet Interrupt Vector Register (IVEC)	6-9
6.2.11	RxBD Active Register (R_DES_ACTIVE)	6-10
6.2.12	TxBD Active Register (X_DES_ACTIVE)	6-11
6.2.13	MII Management Frame Register (MII_DATA)	6-12
6.2.14	MII Speed Control Register (MII_SPEED)	6-14
6.2.15	FIFO Receive Bound Register (R_BOUND)	6-15
6.2.16	FIFO Receive Start Register (R_FSTART)	6-16
6.2.17	Transmit Watermark Register (X_WMRK	6-16
6.2.18	FIFO Transmit Start Register (X_FSTART)	6-17
6.2.19	DMA Function Code Register (FUN_CODE)	6-18
6.2.20	Receive Control Register (R_CNTRL)	6-19
6.2.21	Receive Hash Register (R_HASH)	6-20
6.2.22	Transmit Control Register (X_CNTRL)	6-21
6.3	Initialization Sequence	6-22
iv	MPC860T (Rev. D) Fast Ethernet Controller Supplement	MOTOROLA
	PRELIMINARYÑSUBJECTFor ore nformation On This Product,
	TO CHANGE WITHOUT NOTICE

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