MPC860T Pin Assignments | Freescale Semiconductor manual

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

7.4 MPC860T Pin Assignments

Figure 7-5 shows the MPC860T pin assignments. Pins that support the FEC are shown in black.

W

M_RxD0M_Rx_CLKM_TxD1M_Tx_CLK D0

D4

D1

D2

D3

D5

VDDL

D6

D7

D29

DP2 CLKOUT IPA3

V

M_RxD2M_RxD1M_TxD0M_Rx_DVM_Tx_EN IRQ0 D13

D27

D10

D14

D18

D20

D24

D28

DP1

DP3

DP0

NC VSSSYN1

U

PA0

PB14 M_RxD3M_TxD2M_TxD3 IRQ1

D8

D23

D11

D16

D19

D21

D26

D30

IPA5

IPA4

IPA2

NC

VSSSYN

T

PA1

PC5

PC4 M_Tx_ER M_Rx_ER VDDH D12

D17

D9

D15

D22

D25

D31

IPA6

IPA0

IPA1

IPA7

XFC VDDSYN

VDDH

R

PC6

PA2

PB15

MDC

VDDH WAIT_B WAIT_APORESETKAPWR

P

PA4

PB17

PA3

VDDH

GND

GND

VDDHRSTCONFSRESETXTAL

N

PB19

PA5

PB18

PB16

HRESETTEXP EXTCLKEXTAL

M

PA7

PC8

PA6

PC7

MODCK2BADDR28BADDR29VDDL

L

PB22

PC9

PA8

PB20

OP0

AS

OP1 MODCK1

K

PC10

PA9

PB23

PB21

GND

BADDR30 IPB6 ALEA

IRQ4

J

PC11

PB24

PA10

PB25

IPB5

IPB1

IPB2

ALEB

H

VDDL M_MDIO

TDI

TCK

M_COL

IRQ2

IPB0

IPB7

G

TRESET TMS

TDO

PA11

GND

GND

BR

IRQ6

IPB4

IPB3

F

PB26

PC12

PA12

VDDH

VDDH

VDDH

VDDH

TS

IRQ3 BURST

E

PB27

PC13

PA13

PB29

CS3

BI

BG

BB

D

PB28

PC14

PA14

PC15

A8

NC

NC

A15

A19

A25

A18

BSA0 GPLA0

NC

CS6

CS2

GPLA5

BDIP

TEA

C

PB30

PA15

PB31

A3

A9

A12

A16

A20

A24

A26

TSIZ1

BSA1

WE0

GPLA1 GPLA3

CS7

CS0

TA

GPLA4

B

A0

A1

A4

A6

A10

A13

A17

A21

A23

A22

TSIZ0

BSA3 M_CRS

WE2

GPLA2

CS5

CE1A

WR

GPLB4

A

A2

A5

A7

A11

A14

A27

A29

A30

A28

A31

VDDL

BSA2

WE1

WE3

CS4

CE2A

CS1

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Figure 7-5. MPC860T Pinout DiagramÑTop View

The following pins are marked as spare on the 860:

¥B7: SPARE1/MII_CRS

¥H18: SPARE2/MII_MDIO

¥V15: SPARE3/MII_TX_EN

¥H4: SPARE4/MII_COL

MOTOROLAChapter 7.Electrical Characteristics7-5

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

Go to: www.freescale.com

Image 65

Freescale Semiconductor user manual MPC860T Pin Assignments, Following pins are marked as spare on

Contents

Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet Controller Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number Illustrations Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision History Comparison with the MPC860 Features 1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System Design Inc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miimdc L1RSYNCBRXD3 Miitxer MIITXD2 REJECT3REJECT4 MIITXD1 Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FEC FEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0 FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table Algorithm Collision Handling Inter-Packet Gap Time Transmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External Loopback Reception Errors Port D Pin Functions Chapter Parallel I/O Ports Signal Function Enabling MII ModePort D Registers Shows the port D pin assignments CLK Sdma Registers Sdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID Bits Brießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description Section RAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh Þelds Describes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions Hashhigh Beginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart Þelds Xdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field Descriptions Describes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions Fecpinmux Rfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr 11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions Ilevel 12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata Þelds 15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed 17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field Descriptions Transmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field Descriptions 19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 21 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo 22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej 22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field Descriptions Initialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware Initialization Descriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step Description Buffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step 27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO1 29 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSL Data Xcntrlhbc = Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcations MII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max Unit MII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COL MII Serial Management Channel Timing Shows the MII serial management channel timing diagram MPC860T Pin Assignments Following pins are marked as spare on Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product