Freescale Semiconductor MPC860T user manual Shows the MII serial management channel timing diagram

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Freescale Semiconductor, Inc.

7.3.4 MII Serial Management Channel Timing (MDIO,MDC)

Table 7-4 provides information on the MII serial management channel signal timing, shown in Figure 7-4. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 7-4. MII Serial Management Channel Timing

Num	Characteristic	Min	Max	Unit
		(ns)	(ns)
M10	MDC falling edge to MDIO output invalid (minimum	0	Ñ	ns
	propagation delay)
M11	MDC falling edge to MDIO output valid (max prop delay)	Ñ	25
M12	MDIO (input) to MDC rising edge setup	10	Ñ	ns
M13	MDIO (input) to MDC rising edge hold	0	Ñ
M14	MDC pulse width high	40%	60%	MDC period
M15	MDC pulse width low	40%	60%	MDC period

Figure 7-4 shows the MII serial management channel timing diagram.

Freescale Semiconductor,

MDC (output)

MDIO (output)

MDIO (input)

M12

M14

MM15

M10

M11

M13

Figure 7-4. MII Serial Management Channel Timing Diagram

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