Freescale Semiconductor MPC860T Transmit Control Register Xcntrl, describes Rhash Þelds

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-22 describes R_HASH Þelds.

Table 6-23. R_HASH Field Descriptions

Bits	Name	Description
0Ð7	Ñ	Reserved for internal use. When read, these bits are unpredictable.
8Ð20	Ñ	Reserved. These bits are read as zeros.
21Ð31	MAX_FRAME_LENGTH	User read/write Þeld. Resets to decimal 1518. Length is measured starting at DA
		and includes the CRC at the end of the frame. Transmit frames longer than
		MAX_FRAME_LENGTH cause an BABT interrupt. Receive frames longer than
		MAX_FRAME_LENGTH cause a BABR interrupt and set the LG bit in the
		end-of-frame BD. The recommended value to be programmed by the user is 1518
		or 1522 (if VLAN tags are supported).

6.2.22 Transmit Control Register (X_CNTRL)

The transmit control register (X_CNTRL), shown in Figure 6-22, is written by the user to conÞgure the transmit block.

Bits	0	1	2	3	4	5	6	7		8	9	10	11	12	13	14	15
Field									Ñ
Reset							0000_0000_0000_0000
R/W								Read/write
Addr								0xF84
Bits	16	17	18	19	20	21	22	23		24	25	26	27	28	29	30	31
Field							Ñ								FDEN	HBC	GTS
Reset							0000_0000_0000_0000
R/W								Read/write
Addr								0xF86

Figure 6-22. X_CNTRL Register

Table 6-24 describes X_CNTRL Þelds.

		Table 6-24. X_CNTRL Field Descriptions
Bits	Name	Description
0Ð28	Ñ	Reserved. These bits read as zero.
29	FDEN	Full-duplex enable. If set, frames are transmitted independently of carrier sense and collision
		inputs. This bit should be modiÞed only when ECNTRL[ETHER_EN] is cleared.
30	HBC	Heartbeat control. If HBC = 1 and FDEN = 0, the heartbeat check is performed after transmission
		and TxBD[HB] and IEVENT[HBERR] are set, if the collision input does not assert within the
		heartbeat window. HBC should be modiÞed only when ECNTRL[ETHER_EN] is cleared.

MOTOROLAChapter 6.Programming Model6-21

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