Receive Control Register Rcntrl | Freescale Semiconductor MPC860T

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		Freescale Semiconductor, Inc.
Table 6-21 describes FUN_CODE Þelds.
		Table 6-21. FUN_CODE Field Descriptions

Bits	Name	Description

0	Ñ	Reserved. This bit reads as zero.

1Ð2	DATA_BO	Byte order. Supplied to the SDMA interface during receive and transmit data DMA transfers.
		00 Reserved
		01 PowerPC little-endian byte ordering. Considering each double word in the buffer, data bytes
		is received to or transmitted from address 0b111 to 0b000. This is to conform to the
		double-word address munging performed for byte transfers (because communication is
		byte-oriented).
		1x Big-endian (Motorola) or true little-endian (DEC or Intel) byte ordering. Considering each
		word in the buffer, data bytes are received or transmitted from address 0b00 to 0b11. This is
		because communication is byte-oriented, and byte reads and writes are identical in big- and
		little-endian modes

3Ð4	DESC_BO	The byte order Þeld supplied to the SDMA interface during receive and transmit open descriptor
		DMA transfers, and during close descriptor DMA transfers.
		00 Reserved
		01 PowerPC little-endian byte ordering. Considering each double word in the buffer, data bytes
		are received or transmitted from address 0b111 to 0b000. This conforms to the double-word
		address munging performed for byte transfers (since communication is byte-oriented).
		1x Big-endian (Motorola) or true little-endian (DEC or Intel) byte ordering. Considering each
		word in the buffer, data bytes are received or transmitted from address 0b00 to 0b11. [This
		is because reception or transmission in communications is byte-oriented and byte reads
		and writes are identical in big-endian and little-endian modes].

5Ð7	FC	The function code Þeld supplied to the SDMA interface during all DMA transfers.

8Ð31	Ñ	Reserved. These bits read as zero.

6.2.20 Receive Control Register (R_CNTRL)

The R_CNTRL register, shown in Figure 6-20, is programmed by the user to control the operational mode of the receive block.

Bits	0	1	2	3	4	5	6	7	8		9		10		11	12	13	14	15

Field										Ñ

Reset								0000_0000_0000_0000

R/W									Read/write

Addr										0xF34

Bits	16	17	18	19	20	21	22	23	24		25		26		27	28	29	30	31

Field						Ñ								BC_REJ		PROM	MII_MODE	DRT	LOOP

Reset								0000_0000_0000_0000

R/W									Read/write

Addr										0xF36

Figure 6-20. R_CNTRL Register

MOTOROLAChapter 6.Programming Model6-19

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Freescale Semiconductor MPC860T Receive Control Register Rcntrl, describes Funcode Þelds, Funcode Field Descriptions

Contents

Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet Controller Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number Illustrations Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision HistoryOverview Lists signiÞcant changes between revisions of this document Comparison with the MPC860 Features 1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller SIU Interrupt ConÞguration Glueless System Design Inc Signal Descriptions FEC Signal DescriptionsName Pin Description Miitxer L1RSYNCBMiimdc RXD3 MIITXD1 REJECT3MIITXD2 REJECT4 Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver Connection RXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0 FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Rcntrlprom = Hash Table Algorithm Collision Handling Inter-Packet Gap Time Internal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception Errors Reception Errors Port D Pin Functions Chapter Parallel I/O Ports Shows the port D pin assignments Enabling MII ModeSignal Function Port D Registers CLK Sdma Registers Bits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAID Address Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory Map RAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow Þelds Hashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field Descriptions Describes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow Þelds Receive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize Þelds Fecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field Descriptions Hberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field Descriptions Ilevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field Descriptions TxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds Dispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions 17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register 18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart Þelds Fifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field Descriptions Descbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field Descriptions Bcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions 23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds 25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware Initialization Step Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting Ecntrletheren Step 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBD RO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data Length TO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field Descriptions Data Xcntrlhbc = Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Num Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal Timing CRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen Txer MII Serial Management Channel Timing Shows the MII serial management channel timing diagram MPC860T Pin Assignments Following pins are marked as spare on Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product