MPC860T Rev. D Fast Ethernet Controller
Freescale Semiconductor, Inc
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Contents
Parallel I/O Ports
Contents
Paragraph Title Number
Illustrations
Title Number
Viii MPC860T Rev. D Fast Ethernet Controller Supplement
Tables
Number
Lists signiÞcant changes between revisions of this document
Document Revision History
Overview
Document Revision History
Features
Comparison with the MPC860
1 MPC860TBlock Diagram
Embedded PowerPC Processor Core
System Interface Unit SIU
Fast Ethernet Controller
Glueless System Design
SIU Interrupt ConÞguration
Inc
Signal Descriptions
FEC Signal Descriptions
Name Pin Description
RXD3
L1RSYNCB
Miimdc
Miitxer
REJECT4
REJECT3
MIITXD2
MIITXD1
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Transceiver Connection
MII Signals
Signal Description FEC Signal Name
This chapter discusses the operation of the FEC
TXD0
Serial Mode Connections to the External Transceiver
FEC Frame Transmission
RXD0
FEC Frame Reception
FEC Command Set
CAM Interface
Ethernet Address Recognition
Hash Table Algorithm
Rcntrlprom =
Inter-Packet Gap Time
Collision Handling
Reception Errors
Ethernet Error-Handling Procedure
Transmission Errors
Internal and External Loopback
Reception Errors
Chapter Parallel I/O Ports
Port D Pin Functions
Port D Registers
Enabling MII Mode
Signal Function
Shows the port D pin assignments
Sdma Registers
CLK
FRZ Faid RAID
Describes Sdcr Þelds
Sdcr Field Descriptions
Bits
FEC Parameter RAM Memory Map
Parameter RAM
Brießy describes each enter in the FEC parameter RAM
Address Name Description Section
RAM Perfect Match Address Low Register Addrlow
Describes the Addrlow Þelds
RAM Perfect Match Address High Addrhigh
RAM Hash Table High Hashtablehigh
Describes the Addrhigh Þelds
Hashtablehigh Field Descriptions
RAM Hash Table Low Hashtablelow
Describes Hashtablehigh Þelds
Hashhigh
Describes Hashtablelow Þelds
Beginning of RxBD Ring Rdesstart
Beginning of TxBD Ring Xdesstart
Describes Rdesstart Þelds
Receive Buffer Size Register Rbuffsize
Describes Xdesstart Þelds
Xdesstart Field Descriptions
Describes Rbuffsize Þelds
Spare Fecpin Etheren Reset MUX
Ethernet Control Register Ecntrl
Rbuffsize Field Descriptions
Ecntrl Field Descriptions
Interrupt Event IEVENT/Interrupt Mask Register Imask
Describes Ecntrl Þelds
Fecpinmux
10. IEVENT/IMASK Field Descriptions
Ethernet Interrupt Vector Register Ivec
Rfint to notify at the end of frame
Hberr
11. Ivec Field Descriptions
RxBD Active Register Rdesactive
11 describes Ivec Þelds
Ilevel
TxBD Active Register Xdesactive
12 describes Rdesactive Þelds
12. Rdesactive Field Descriptions
MII Management Frame Register Miidata
13 describes Xdesactive Þelds
13. Xdesactive Field Descriptions
14 describes Miidata Þelds
14. Miidata Field Descriptions
15. Miispeed Field Descriptions
MII Speed Control Register Miispeed
15 describes Miispeed Þelds
Dispreamble Miispeed
16. Programming Examples for Miispeed Register
Fifo Receive Bound Register Rbound
17 describes Rbound Þelds
17. Rbound Field Descriptions
18 describes Rñfstart Þelds
Fifo Receive Start Register Rfstart
Transmit Watermark Register Xwmrk
18. Rfstart Field Descriptions
Fifo Transmit Start Register Xfstart
19 bit Þeld descriptions for Xwmrk
19. Xwmrk Field Descriptions
20. Xfstart Field Descriptions
DMA Function Code Register Funcode
20 describes Xfstart Þelds
DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3
21. Funcode Field Descriptions
Receive Control Register Rcntrl
21 describes Funcode Þelds
Descbo
22. Rcntrl Field Descriptions
Receive Hash Register Rhash
22 describes Rcntrl Þelds
Bcrej
24 describes Xcntrl Þelds
Transmit Control Register Xcntrl
22 describes Rhash Þelds
23. Rhash Field Descriptions
Hardware Initialization
User Initialization before Setting Ecntrletheren
Initialization Sequence
25. Hardware Initialization
User Initialization after Asserting Ecntrletheren
27. User Initialization before Setting Ecntrletheren
Descriptor Controller Initialization
Step Description
Ethernet Receive Buffer Descriptor RxBD
27. User Initialization after Setting Ecntrletheren
Buffer Descriptors BDs
Step
RO1 RO2 Data Length
RxBD format is shown in Table
27. Receive Buffer Descriptor RxBD Field Description
RO1
29. Transmit Buffer Descriptor TxBD Field Descriptions
Ethernet Transmit Buffer Descriptor TxBD
29 describes TxBD Þelds
TO1 TO2 DEF CSL
Xcntrlhbc =
Data
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MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk
DC Electrical Characteristics
AC Electrical Characteristics
Electrical SpeciÞcations
MII Transmit Signal Timing
MII Transmit Signal Timing TXD30, TXEN, TXER, Txclk
MII Receive Signal Timing
Num Characteristic Min Max Unit
Txen Txer
MII Async Inputs Signal Timing CRS, COL
MII Async Inputs Signal Timing
CRS, COL
Shows the MII serial management channel timing diagram
MII Serial Management Channel Timing
Following pins are marked as spare on
MPC860T Pin Assignments
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Freescale Semiconductor, Inc
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