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Freescale Semiconductor MPC860T Beginning of RxBD Ring Rdesstart, Describes Hashtablelow Þelds

Models: MPC860T

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Table 6-5 describes HASH_TABLE_LOW Þelds.
		Table 6-5. HASH_TABLE_LOW Field Descriptions

Bits	Name	Description

0Ð31	HASH_LOW	Contains the lower 32 bits of the 64-bit hash table used in address recognition for receive
		frames with a multicast address. HASH_LOW[0] contains hash index bit 31. HASH_LOW[31]
		contains hash index bit 0.

6.2.5 Beginning of RxBD Ring (R_DES_START)

The R_DES_START register, shown in Figure 6-5, is like the RBASE register used by other protocols. It provides a pointer to the start of the circular RxBD queue in external memory. This pointer should be quad-word aligned. Bits 30 and 31 should be written to 0 by the user; hardware ignores non-zero values in these bits. This register is written by the user, is not reset, and must be initialized by the user.

Bits	0	1	2	3	4	5		6		7		8		9	10	11	12	13	14		15

Field									R_DES_START

Reset										UndeÞned

R/W										Read/write

Addr										0xE10

Bits	16	17	18	19	20	21		22		23		24		25	26	27	28	29	30		31

Field							R_DES_START													00

Reset										UndeÞned

R/W										Read/write

Addr										0xE12

Figure 6-5. R_DES_START Register

Table 6-6 describes R_DES_START Þelds.

Table 6-6. R_DES_START Field Descriptions

Bits	Name	Description

0Ð29	R_DES_START	Pointer to start of RxBD queue.

30Ð31	Ñ	Reserved. Should be written to zero by the host processor.

6.2.6 Beginning of TxBD Ring (X_DES_START)

The X_DES_START register, shown in Figure 6-6, is like the TBASE register used by other protocols. It provides a pointer to the start of the circular TxBD queue in external memory. This pointer should be quad-word aligned. Bits 30 and 31 should be cleared by the user; hardware ignores non-zero values in these bits. It is written by the user, is not reset, and must be initialized by the user.

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Freescale Semiconductor MPC860T user manual Beginning of RxBD Ring Rdesstart, Beginning of TxBD Ring Xdesstart

Contents

Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features1 MPC860TBlock Diagram System Interface Unit SIU Embedded PowerPC Processor CoreFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc FEC Signal Descriptions Signal DescriptionsName Pin Description Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception CAM Interface FEC Command SetEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsDescribes Xdesstart Þelds Receive Buffer Size Register RbuffsizeXdesstart Field Descriptions Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions Ilevel12 describes Rdesactive Þelds TxBD Active Register Xdesactive12. Rdesactive Field Descriptions 13 describes Xdesactive Þelds MII Management Frame Register Miidata13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field Descriptions19 bit Þeld descriptions for Xwmrk Fifo Transmit Start Register Xfstart19. Xwmrk Field Descriptions 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product