Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-2 describes the ADDR_LOW Þelds.

 

 

Table 6-2. ADDR_LOW Field Descriptions

 

 

 

Bits

Name

Description

 

 

 

0Ð31

ADDR_LOW

Bytes in the 6-byte address: 0 (bits 0Ð7), 1 (bits 8Ð15), 2 (bits 16Ð23) and 3 (bits 24Ð31)

 

 

 

6.2.2 RAM Perfect Match Address High (ADDR_HIGH)

The ADDR_HIGH register, shown in Figure 6-2, is written by and must be initialized by the user. It contains bytes 4 and 5 of the 6-byte address used to compare with the destination address Þeld of the receive frames. Byte 0 is the Þrst byte sent at the start of the frame.

Bits

0

1

2

3

4

5

6

7

 

8

9

10

11

12

13

14

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

ADDR_HIGH BYTE 4

 

 

 

 

 

ADDR_HIGH BYTE 5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

16

17

18

19

20

21

22

23

 

24

25

26

27

28

29

30

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

 

 

 

 

 

 

Ñ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE06

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-2. ADDR_HIGH Register

Table 6-3 describes the ADDR_HIGH Þelds.

Table 6-3. ADDR_HIGH Field Descriptions

Bits

Name

Description

 

 

 

0Ð15

ADDR_HIGH

Bytes of the 6-byte address: 4 (bits 0Ð7) and 5 (bits 8Ð15)

 

 

 

16Ð31

Ñ

Reserved. Should be cleared by the host processor.

 

 

 

6.2.3 RAM Hash Table High (HASH_TABLE_HIGH)

The HASH_TABLE_HIGH register, shown in Figure 6-3, contains the upper 32 bits of the 64-bit hash table used in address recognition for receive frames with a multicast address. It is written by and must be initialized by the user

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Freescale Semiconductor MPC860T user manual RAM Perfect Match Address High Addrhigh, RAM Hash Table High Hashtablehigh