Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
(I_EVENT[BABT] = 1); however, the entire frame is sent (no truncation). Whether buffer or frame interrupts can be generated is determined by I_MASK settings.
To pause transmission, set the graceful transmit stop bit, X_CNTRL[GTS]. When GTS is set, the FEC transmitter stops immediately if no transmission is in progress or continues transmission until the current frame either Þnishes or terminates with a collision. The GRA interrupt occurs when the graceful transmit stop operation completes. When GTS is cleared, the FEC resumes transmission with the next frame.
The FEC transmits bytes lsb Þrst.
3.3 FEC Frame Reception
FEC reception requires almost no host intervention. The FEC can perform address recognition, CRC checking,
When the software driver sets ECNTRL[ETHER_EN] and R_DES_ACTIVE in the CSR RxBD active register (R_DES_ACTIVE), the FEC receiver is enabled and immediately starts processing receive frames. When RX_DV is asserted, the receiver Þrst checks for a valid preamble/SFD (start frame delimiter) header, which is stripped and the frame is processed by the receiver. If a valid header is not found, the frame is ignored.
In serial mode, the Þrst 16 bit times of RX_D0 after RX_DV (RENA) is asserted are ignored. Following the Þrst 16 bit times the data sequence is checked for alternating ones and zeros.
¥If a 11 or 00 sequence is detected during bit times 17 to 21, the rest of the frame is ignored.
¥After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. If a 11 is detected, the preamble/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more preamble bytes may occur, but if a 00 sequence is detected before the SFD byte, the frame is ignored.
After the Þrst eight bytes of the frame are passed to the receive FIFO, the FEC performs address recognition on the frame.
As soon as a collision window (64 bytes) of data is received and if address recognition has not rejected the frame, the FEC starts transferring the incoming frame to the RxBDÕs associated buffer. If the frame is a too short (due to collision) or is rejected by address recognition, no receive buffers are Þlled. Thus, no collision frames are presented to the user, except for any late collisions, which indicate serious LAN problems. When the data buffer has been Þlled, the FEC clears RxBD[E] and generates an RXB interrupt (if I_MASK[RBIEN] is set). If the incoming frame exceeds the length of the data buffer, the FEC fetches the next RxBD in the table and, if it is empty, continues transferring the rest
MOTOROLAChapter 3. Fast Ethernet Controller Operation3-3
PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE
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