Freescale Semiconductor MPC860T Embedded PowerPC Processor Core, System Interface Unit SIU

Freescale Semiconductor, Inc.

Embedded

PowerPC

Processor

Core

Instruction	4-KByte
Bus	Instruction Cache
	Instruction MMU
Load/Store	4-KByte
Bus	Data Cache
	Data MMU

Unified

Bus

System Interface Unit (SIU)

Memory Controller

Internal	External
Bus Interface	Bus Interface
Unit	Unit

System Functions

Real-Time Clock

PCMCIA-ATA Interface

Semiconductor, Inc...

Fast

Ethernet

Controller

DMAs

FIFOs

10/100 Base-T Media Access Control

MII

Parallel I/O	4 Timers		Interrupt	Dual-Port RAM
			Controllers			Serial
Baud Rate
		32-Bit RISC Controller				and
Generators						DMA
			and Program
						Channels
Parallel Interface Port	Timers		ROM		MAC
and UTOPIA

SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C

Time Slot Assigner

Serial Interface

Freescale

Figure 1-1. MPC860T Block Diagram

The FEC complies with the IEEE 802.3 speciÞcation for 10- and 100-Mbps connectivity. Full-duplex 100-Mbps operation is supported at system clock rates of 40 MHz and higher. A 25-MHz system clock supports 10-Mbps operation or half-duplex 100-Mbps operation.

The implementation of bursting DMA reduces bus usage. Independent DMA channels for accessing BDs and transmit and receive data minimize latency and FIFO depth requirements.

Transmit and receive FIFOs further reduce bus usage by localizing all collisions to the FEC. Transmit FIFOs maintain a full collision window of transmit frame data, eliminating the need for repeated DMA over the system bus when collisions occur. On the receive side, a full collision window of data is received before any receive data is transferred into system memory, allowing the FIFO to be ßushed in the event of a runt or collided frame, with no DMA activity. However, external memory for buffers and BDs is required; on-chip FIFOs are designed only to compensate for collisions and for system bus latency.

Independent TxBD and RxBD rings in external memory allow nearly unlimited ßexibility

1-4MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

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