Receive Hash Register Rhash | Freescale Semiconductor MPC860T

Freescale Semiconductor, Inc.

		Freescale Semiconductor, Inc.
Table 6-22 describes R_CNTRL Þelds.
		Table 6-22. R_CNTRL Field Descriptions

Bits	Name	Description

0Ð26	Ñ	Reserved. This bit reads as zero.

27	BC_REJ	Broadcast frame reject.
		If set, frames with DA + 0xFFFF_FFFF_FFFF are rejected unless the PROM bit set. If both
		BC_REJ and PROM = 1, frames with broadcast DA are accepted and RxBD[M] is set.

28	PROM	Promiscuous mode.
		0Promiscuous mode disabled
		1Promiscuous mode enabled. All frames are accepted regardless of address matching.

29	MII_MODE	Selects external interface mode for both transmit and receive blocks.
		0 Selects seven-wire mode (used only for serial 10 Mbps)
		1 Selects MII mode.

30	DRT	Disable receive on transmit.
		0 Receive path operates independently of transmit (use for full duplex or to monitor transmit
		Selects seven-wire mode (used only for serial 10 Mbps)
		1 Disable reception of frames while transmitting (normally used for half-duplex mode)

31	LOOP	Internal loopback. If set, transmitted frames are looped back internal to the device and the
		transmit output signals are not asserted. The system clock is substituted for the TX_CLK when
		LOOP is asserted. DRT must be 0 when asserting LOOP.

6.2.21 Receive Hash Register (R_HASH)

With revision D of the MPC860T silicon, R_HASH[MAX_FRAME_LENGTH], shown in Figure 6-21, is programmable. This field lets the user set the frame length (in bytes) at which the BABR and BABT interrupts and RxBD[LG] should be set. In the B.x revisions of the MPC860T, the value is hard-wired to 1518 bytes.

Bits	0	1	2	3	4	5	6	7		8	9	10	11		12	13	14	15

Field									Ñ

Reset							0000_0000_0000_0000

R/W								Read/write

Addr								0xF48

Bits	16	17	18	19	20	21	22	23		24	25	26	27		28	29	30	31

Field			Ñ							MAX_FRAME LENGTH

Reset							0000_0101_1110_1110

R/W								Read/write

Addr								0xF4A

Figure 6-21. R_HASH Register

6-20MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Image 52

Freescale Semiconductor MPC860T Receive Hash Register Rhash, describes Rcntrl Þelds, Rcntrl Field Descriptions, Bcrej

Contents

MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, Inc Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title Number Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History OverviewLists signiÞcant changes between revisions of this document Document Revision History Features Comparison with the MPC860 1 MPC860TBlock Diagram System Interface Unit SIU Embedded PowerPC Processor CoreFast Ethernet Controller Glueless System Design SIU Interrupt ConÞguration Inc FEC Signal Descriptions Signal DescriptionsName Pin Description L1RSYNCB MiimdcRXD3 Miitxer REJECT3 MIITXD2REJECT4 MIITXD1 Freescale Semiconductor, Inc MII Signals Signal Description FEC Signal NameTransceiver Connection This chapter discusses the operation of the FEC Serial Mode Connections to the External Transceiver FEC Frame TransmissionTXD0 RXD0 FEC Frame Reception CAM Interface FEC Command SetEthernet Address Recognition Hash Table Algorithm Rcntrlprom = Inter-Packet Gap Time Collision Handling Ethernet Error-Handling Procedure Transmission ErrorsReception Errors Internal and External Loopback Reception Errors Chapter Parallel I/O Ports Port D Pin Functions Enabling MII Mode Signal FunctionPort D Registers Shows the port D pin assignments Sdma Registers CLK Describes Sdcr Þelds Sdcr Field DescriptionsFRZ Faid RAID Bits Parameter RAM Brießy describes each enter in the FEC parameter RAMFEC Parameter RAM Memory Map Address Name Description Section RAM Perfect Match Address Low Register Addrlow RAM Perfect Match Address High Addrhigh RAM Hash Table High HashtablehighDescribes the Addrlow Þelds Describes the Addrhigh Þelds RAM Hash Table Low Hashtablelow Describes Hashtablehigh ÞeldsHashtablehigh Field Descriptions Hashhigh Beginning of RxBD Ring Rdesstart Beginning of TxBD Ring XdesstartDescribes Hashtablelow Þelds Describes Rdesstart Þelds Describes Xdesstart Þelds Receive Buffer Size Register RbuffsizeXdesstart Field Descriptions Spare Fecpin Etheren Reset MUX Ethernet Control Register EcntrlDescribes Rbuffsize Þelds Rbuffsize Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register Imask Describes Ecntrl ÞeldsEcntrl Field Descriptions Fecpinmux Ethernet Interrupt Vector Register Ivec Rfint to notify at the end of frame10. IEVENT/IMASK Field Descriptions Hberr RxBD Active Register Rdesactive 11 describes Ivec Þelds11. Ivec Field Descriptions Ilevel 12 describes Rdesactive Þelds TxBD Active Register Xdesactive12. Rdesactive Field Descriptions 13 describes Xdesactive Þelds MII Management Frame Register Miidata13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field Descriptions MII Speed Control Register Miispeed 15 describes Miispeed Þelds15. Miispeed Field Descriptions Dispreamble Miispeed Fifo Receive Bound Register Rbound 17 describes Rbound Þelds16. Programming Examples for Miispeed Register 17. Rbound Field Descriptions Fifo Receive Start Register Rfstart Transmit Watermark Register Xwmrk18 describes Rñfstart Þelds 18. Rfstart Field Descriptions 19 bit Þeld descriptions for Xwmrk Fifo Transmit Start Register Xfstart19. Xwmrk Field Descriptions DMA Function Code Register Funcode 20 describes Xfstart Þelds20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 Receive Control Register Rcntrl 21 describes Funcode Þelds21. Funcode Field Descriptions Descbo Receive Hash Register Rhash 22 describes Rcntrl Þelds22. Rcntrl Field Descriptions Bcrej Transmit Control Register Xcntrl 22 describes Rhash Þelds24 describes Xcntrl Þelds 23. Rhash Field Descriptions User Initialization before Setting Ecntrletheren Initialization SequenceHardware Initialization 25. Hardware Initialization 27. User Initialization before Setting Ecntrletheren Descriptor Controller InitializationUser Initialization after Asserting Ecntrletheren Step Description 27. User Initialization after Setting Ecntrletheren Buffer Descriptors BDsEthernet Receive Buffer Descriptor RxBD Step RxBD format is shown in Table 27. Receive Buffer Descriptor RxBD Field DescriptionRO1 RO2 Data Length RO1 Ethernet Transmit Buffer Descriptor TxBD 29 describes TxBD Þelds29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSL Xcntrlhbc = Data Freescale Semiconductor, Inc DC Electrical Characteristics AC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcations MII Transmit Signal Timing TXD30, TXEN, TXER, Txclk MII Receive Signal TimingMII Transmit Signal Timing Num Characteristic Min Max Unit MII Async Inputs Signal Timing CRS, COL MII Async Inputs Signal TimingTxen Txer CRS, COL Shows the MII serial management channel timing diagram MII Serial Management Channel Timing Following pins are marked as spare on MPC860T Pin Assignments Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product