Freescale Semiconductor MPC860T FEC Frame Transmission, TXD0, RXD0, TXER, TXD31, MDC, Mdio

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 3-2. Serial Mode Connections to the External Transceiver

Signal Description	FEC Signal Name
Transmit clock	TX_CLK
Transmit enable	TX_EN
Transmit data	TXD0
Collision	COL
Receive clock	RX_CLK
Receive enable	RX_DV
Receive Data	RXD0
Unused 860T inputsÑTie to ground	RX_ER, CRS, RXD[3:1]
Unused 860T outputsÑIgnore	TX_ER, TXD[3:1], MDC, MDIO

3.2 FEC Frame Transmission

FEC transmissions require almost no host intervention. When the software driver sets the ETHER_EN bit in the Ethernet control register (ECNTRL) and the X_DES_ACTIVE bit in the CSR TxBD active register (X_DES_ACTIVE), the FEC is enabled and fetches the Þrst TxBD. If the user has a frame ready to transmit, a DMA transfer of the transmit data buffers begins immediately.

A 512-bit collision window of transmit data is sent to the transmit FIFO before transmission begins. If the line is not busy, the MAC transmit logic asserts TX_EN and sends the preamble sequence, the start frame delimiter (SFD), and then the frame information. If the line is busy, the controller waits for the carrier sense signal, CRS, to remain inactive for 60 bit times. Transmission begins after an additional 36 bit times (96 bit times after CRS became inactive).

If a collision occurs during the transmit frame, the FEC follows the speciÞed backoff procedures and tries retransmitting the frame until the retry limit threshold is reached. The FEC stores the Þrst 64 bytes of the transmit frame in internal RAM so that they do not have to be retrieved from system memory in case of a collision. This improves bus usage and latency in case the backoff timer output causes a need for an immediate retransmission.

When the end of the current BD is reached and TxBD[L] is set, the frame check sequence (32-bit CRC) is appended (if TxBD[TC] = 1) and TX_EN is negated. After the frame check sequence is sent, the FEC writes the frame status bits into the BD and clears the R bit. When the end of the current BD is reached and the L bit is not set (a frame consists of multiple buffers), only the R bit is cleared. Short frames are automatically padded by the transmit logic.

A transmit frame length exceeding the value set for MAX_FRAME_LENGTH in the

receive	hash register (R_HASH) generates a babbling transmit	interrupt
3-2	MPC860T (Rev. D) Fast Ethernet Controller Supplement	MOTOROLA
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