National CP3BT26 manual Master Bus Stall, Repeated Start, Master Error Detections, Slave Mode

CP3BT26

Master Bus Stall

The ACB module can stall the ACCESS.bus between trans- fers while waiting for the core’s response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowl- edge cycle. Note that this is interpreted as the beginning of the following bus operation. Software must make sure that the next operation is prepared before the bit that causes the bus stall is cleared.

The bits that can cause a stall in master mode are:

„Negative acknowledge after sending a byte (ACBSTNEGACK = 1).

„ACBST.SDAST bit is set.

„If the ACBCTL1.STASTRE bit is set, after a successful start (ACBST.STASTR = 1).

Repeated Start

A repeated start is performed when this device is already the bus master (ACBST.MASTER = 1). In this case, the AC- CESS.bus is stalled and the ACB waits for the core handling due to: negative acknowledge (ACBST.NEGACK = 1), emp- ty buffer (ACBST.SDAST = 1), or a stop-after-start (ACB- ST.STASTR = 1).

For a repeated start:

1.Set the ACBCTL1.START bit.

2.In master receive mode, read the last data item from the ACBSDA register.

3.Follow the address send sequence, as described in “Sending the Address Byte” on page 183.

4.If the ACB was waiting for handling due to ACB- ST.STASTR = 1, clear it only after writing the requested address and direction to the ACBSDA register.

Master Error Detections

The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the ac- knowledge cycle) and a conflict on the data lines of the AC- CESS.bus. If an illegal action is detected, the BER bit is set, and the MASTER mode is exited (the MASTER bit is cleared).

Bus Idle Error Recovery

When a request to become the active bus master or a re- start operation fails, the ACBST.BER bit is set to indicate the error. In some cases, both this device and the other device may identify the failure and leave the bus idle. In this case, the start sequence may not be completed and the AC- CESS.bus may remain deadlocked.

To recover from deadlock, use the following sequence:

1.Clear the ACBST.BER and ACBCST.BB bits.

2.Wait for a time-out period to check that there is no other active master on the bus (i.e., the ACBCST.BB bit re- mains clear).

3.Disable, and re-enable the ACB to put it in the non-ad- dressed slave mode.

4.At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master by issuing a Start Condition and sends an address field; then issue a Stop Condition to synchronize all the slaves.

24.2.2Slave Mode

A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled, and it is not acting as a master (i.e., ACBST.MASTER = 0), it acts as a slave device.

Once a Start Condition on the bus is detected, this device checks whether the address sent by the current master matches either:

„The ACBADDR.ADDR value if the ACBADDR.SAEN bit is set.

„The ACBADDR2.ADDR value if the ACBADDR2.SAEN bit is set.

„The general call address if the ACBCTL1.GCM bit is set.

This match is checked even when the ACBST.MASTER bit is set. If a bus conflict (on SDA or SCL) is detected, the ACBST.BER bit is set, the ACBST.MASTER bit is cleared, and this device continues to search the received message for a match. If an address match, or a global match, is de- tected:

1.This device asserts its data pin during the acknowledge cycle.

2.The ACBCST.MATCH, ACBCST.MATCHAF (or ACBCST.GCMTCH if it is a global call address match, or ACBCST.ARPMATCH if it is an ARP address), and ACBST.NMATCH in the ACBCST register are set. If the ACBST.XMIT bit is set (i.e., slave transmit mode), the ACBST.SDAST bit is set to indicate that the buffer is empty.

3.If the ACBCTL1.INTEN bit is set, an interrupt is gener- ated if both the INTEN and NMINTE bits in the ACBCTL1 register are set.

4.Software then reads the ACBST.XMIT bit to identify the direction requested by the master device. It clears the ACBST.NMATCH bit so future byte transfers are identi- fied as data bytes.

Slave Receive and Transmit

Slave Receive and Transmit are performed after a match is detected and the data transfer direction is identified. After a byte transfer, the ACB extends the acknowledge clock until software reads or writes the ACBSDA register. The receive and transmit sequence are identical to those used in the master routine.

Slave Bus Stall

When operating as a slave, this device stalls the AC- CESS.bus by extending the first clock cycle of a transaction in the following cases:

—The ACBST.SDAST bit is set.

—The ACBST.NMATCH, and ACBCTL1.NMINTE bits are set.

Slave Error Detections

The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle). When an illegal Start or Stop Condition is detected, the BER bit is set and the MATCH and GMATCH bits are cleared, causing the module to be an unaddressed slave.

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