National CP3BT26 manual ACB Control Register 2 ACBCTL2, ACB Control Register 3 ACBCTL3

CP3BT26

INTEN	The Interrupt Enable bit controls generating
	ACB interrupts. When the INTEN bit is cleared
	ACB interrupt is disabled. When the INTEN bit
	is set, interrupts are enabled.
	0 – ACB interrupts disabled.
	1 – ACB interrupts enabled.
	An interrupt is generated (the interrupt signals
	to the ICU is high) on any of the following
	events:
	„	An address MATCH is detected (ACB-
		ST.NMATCH = 1) and the NMINTE bit is
		set.
	„ A Bus Error occurs (ACBST.BERR = 1).
	„	Negative acknowledge after sending a
		byte (ACBST.NEGACK = 1).
	„ An interrupt is generated on acknowledge
		of each transaction (same as hardware
		setting the ACBST.SDAST bit).
	„	If ACBCTL1.STASTRE = 1, in master
		mode after a successful start
		(ACBST.STASTR = 1).
	„	Detection of a Stop Condition while in
		slave receive mode (ACBST.SLVSTP = 1).
ACK	The Acknowledge bit holds the value this de-
	vice sends in master or slave mode during the
	next acknowledge cycle. Setting this bit to 1
	instructs the transmitting device to stop send-
	ing data, since the receiver either does not
	need, or cannot receive, any more data. This
	bit is cleared after the first acknowledge cycle.
	This bit is ignored when in transmit mode.
GCMEN	The Global Call Match Enable bit enables the
	match of an incoming address byte to the gen-
	eral call address (Start Condition followed by
	address byte of 00h) while the ACB is in slave
	mode. When cleared, the ACB does not re-
	spond to a global call.
	0 – Global call matching disabled.
	1 – Global call matching enabled.
NMINTE	The New Match Interrupt Enable controls
	whether ACB interrupts are generated on new
	matches. Set the NMINTE bit to enable the in-
	terrupt on a new match (i.e., when ACB-
	ST.NMATCH is set). The interrupt is issued
	only if the ACBCTL1.INTEN bit is set.
	0 – New match interrupts disabled.
	1 – New match interrupts enabled.
STASTRE	The Stall After Start Enable bit enables the
	stall after start mechanism. When enabled,
	the	ACB is stalled after the address byte.

When the STASTRE bit is clear, the ACB- ST.STASTR bit is always clear.

0 – No stall after start.

1 – Stall-after-start enabled.

24.3.5ACB Control Register 2 (ACBCTL2)

The ACBCTL2 register is a byte-wide, read/write register that controls the module and selects the ACB clock rate. At reset, the ACBCTL2 register is cleared.

7	1	0
	SCLFRQ6:0	ENABLE
ENABLE	The Enable bit controls the ACB module.
	When this bit is set, the ACB module is en-
	abled. When the Enable bit is clear, the ACB
	module is disabled, the ACBCTL1, ACBST,
	and ACBCST registers are cleared, and the
	clocks are halted.
	0 – ACB module disabled.
	1 – ACB module enabled.
SCLFRQ	The SCL Frequency field specifies the SCL
	period (low time and high time) in master
	mode. The clock low time and high time are
	defined as follows:

tSCLl = tSCLh = 2 × SCLFRQ × tCLK

Where tCLK is this device’s clock period when in Active mode. The SCLFRQ field may be programmed to values in the range of 0001000b through 1111111b. Using any other value has unpredictable results.

24.3.6ACB Control Register 3 (ACBCTL3)

The ACBCTL3 register is a byte-wide, read/write register that expands the clock prescaler field and enables ARP matches. At reset, the ACBCTL3 register is cleared.

7		3	2	1	0
	Reserved		ARPMEN	SCLFRQ8:7
ARPMEN	The ARP	Match Enable bit enables the
	matching of an incoming address byte to the
	SMBus ARP address 110 0001b general call
	address (Start condition followed by address
	byte of 00h), while the ACB is in slave mode.
	0 – ACB does not respond to ARP address-
	es.
	1 – ARP address matching enabled.
SCLFRQ	The SCL Frequency field specifies the SCL
	period (low	time	and high	time) in	master

mode. The ACBCTL3 register provides a 2-bit expansion of this field, with the remaining 7 bits being held in the ACBCTL2 register.

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