National CP3BT26 manual Watchdog Programming Procedure, TWMT0 Control and Status Register T0CSR

25.4.4TWMT0 Control and Status Register (T0CSR)

The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status. At reset, the non-reserved bits of the register are cleared. The register format is shown below.

7	5	4		3	2	1	0
Reserved		FRZT0E	WDLTD		T0INTE	TC	RST
RST	The Restart bit is used to reset Timer T0.
	When this bit is set, it forces the timer to re-
	load the value in the TWMT0 register on the
	next rising edge of the selected input clock.
	The RST bit is reset automatically by the hard-
	ware on the same rising edge of the selected
	input clock. Writing a 0 to this bit position has
	no effect. At reset, the non-reserved bits of the
	register are cleared.
	0	– Writing 0 has no effect.
	1	– Writing 1 resets Timer T0.
TC	The Terminal Count bit is set by hardware
	when the Timer T0 count reaches zero and is
	cleared when software reads the T0CSR reg-
	ister. It is a read-only bit. Any data written to
	this bit position is ignored. The TC bit is not
	cleared if FREEZE mode is asserted by an ex-
	ternal debugging system.
	0	– Timer T0 did not count down to 0.
	1	– Timer T0 counted down to 0.
T0INTE	The Timer T0 Interrupt Enable bit enables an
	interrupt to the CPU each time the Timer T0
	count reaches zero. When this bit is clear,
	Timer T0 interrupts are disabled.
	0	– Timer T0 interrupts disabled.
	1	– Timer T0 interrupts enabled.
WDLTD	The Watchdog Last Touch Delay bit is set
	when either WDCNT or WDSDM is written
	and the data transfer to the Watchdog is in
	progress (see WDCNT and WDSDM register
	description). When clear, it is safe to switch to
	Power Save mode.
	0	– No data transfer to the Watchdog is in
		progress, safe to enter Power Save mode.
	1	– Data transfer to the Watchdog in
		progress.
FRZT0E	The Freeze Timer0 Enable bit controls wheth-
	er TImer 0 is stopped in FREEZE mode. If this
	bit is set, the Timer 0 is frozen (stopped) when
	the FREEZE input to the TWM is asserted. If
	the FRZT0E bit is clear, only the Watchdog
	timer is frozen by asserting the FREEZE input
	signal. After reset, this bit is clear.
	0	– Timer T0 unaffected by FREEZE mode.
	1	– Timer T0 stopped in FREEZE mode.

25.4.5Watchdog Count Register (WDCNT)

The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the Watchdog counter each time the Watchdog is serviced. The Watchdog is start- ed by the first write to this register. Each successive write to this register restarts the Watchdog count with the written value. At reset, this register is initialized to 0Fh.

7 0

PRESET

25.4.6Watchdog Service Data Match Register (WDSDM)

The WSDSM register is a byte-wide, write-only register used for servicing the Watchdog. When this type of servic- ing is enabled (TWCFG.WDSDME = 1), the Watchdog is serviced by writing the value 5Ch to the WSDSM register. Each such servicing reloads the Watchdog counter with the value previously written to the WDCNT register. Writing any data other than 5Ch triggers a Watchdog error. Writing to the register more than once in one Watchdog clock cycle also triggers a Watchdog error signal. If this type of servic- ing is disabled (TWCFG.WDSDME = 0), any write to the WSDSM register is ignored.

7 0

RSTDATA

25.5WATCHDOG PROGRAMMING PROCEDURE

The highest level of protection against software errors is achieved by programming and then locking the Watchdog registers and using the WDSDM register for servicing. This is the procedure:

1.Write the desired values into the TWM Clock Prescaler register (TWCP) and the TWM Timer 0 register (TWMT0) to control the T0IN and T0OUT clock rates. The frequency of T0IN can be programmed to any of

six frequencies ranging from 1/32 × fSLCLK to fSLCLK. The frequency of T0OUT is equal to the frequency of T0IN divided by (1+ PRESET), in which PRESET is the value written to the TWMT0 register.

2.Configure the Watchdog clock to use either T0IN or T0OUT by setting or clearing the TWCFG.WDCT0I bit.

3.Write the initial value into the WDCNT register. This starts operation of the Watchdog and specifies the maximum allowed number of Watchdog clock cycles between service operations.

4.Set the T0CSR.RST bit to restart the TWMT0 timer.

5.Lock the Watchdog registers and enable the Watchdog Service Data Match Enable function by setting bits 0, 1, 2, 3, and 5 in the TWCFG register.

6.Service the Watchdog by periodically writing the value 5Ch to the WDSDM register at an appropriate rate. Servicing must occur at least once per period pro- grammed into the WDCNT register, but no more than once in a single Watchdog input clock cycle.

CP3BT26

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