National CP3BT26 manual Triple Clock and Reset Module

11.0 Triple Clock and Reset

The Triple Clock and Reset module generates a 12 MHz		Clock prescalers to generate two additional low-speed
Main Clock and a 32.768 kHz Slow Clock from external		clocks, and a 32-kHz oscillator start-up delay.
crystal networks or external clock sources. It provides vari-		Figure 4 is block diagram of the Triple Clock and Reset mod-
ous clock signals for the rest of the chip. It also provides the
		ule.
main system reset signal, a power-on reset function, Main
	TWM (Invalid Watchdog Service)			Device Reset
	Flash Interface (Program/Erase Busy)
			Reset
	External Reset
			Module
				Stretched
Reset				Reset

		Power-On-Reset
		Module (POR)
	Stop Main Osc.			Stop Main Osc
		Preset
X1CKI
		Start-Up-Delay		Good Main Clock
		14-Bit Timer
X1CKO	High Frequency
		4-Bit Aux1
	Oscillator			Auxiliary Clock 1
		Prescaler
		4-Bit Aux2		Auxiliary Clock 2
		Prescaler
Main Clock	Div.	8-Bit
	by 2	Prescaler	Mux
	Slow Clock Prescaler			Slow Clock
	Low Frequency
X2CKI	Oscillator			Slow Clock
				Select
		Start-Up-Delay	Time-out	Good Slow Clock
		8-Bit Timer
X2CKO		Preset
				Stop Slow Osc
				Bypass
				32 kHz Osc
			Fast Clock
			Prescaler
		Mux	4-Bit	System Clock
			Prescaler
				Fast Clock
				Select
	Mux			PLL Clock
	PLL
	(x3, x4, or x5)
				Bypass PLL
				Good PLL Clock
		Stop PLL		Stop PLL
				DS006

Figure 4. Triple Clock and Reset Module

CP3BT26

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