Main
CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces
PRELIMINARY
CP3BT26 Reprogrammable Connectivity Processor with Bluetooth, USB, and CAN Interfaces
1.0 General Description
Block Diagram
CP3BT26
Table of Contents
6.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.0 System Configuration Registers . . . . . . . . . . . . . . . 29
8.0 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.0 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.0 Features
3.0 Device Overview
3.1 CR16C CPU CORE
3.2 MEMORY
3.3 INPUT/OUTPUT PORTS
3.4 BUS INTERFACE UNIT
3.7 BLUETOOTH LLC
3.8 USB
3.9 CAN INTERFACE
3.10 QUAD UART
3.11 ADVANCED AUDIO INTERFACE
CP3BT26
3.14 RANDOM NUMBER GENERATOR
3.15 MICROWIRE/SPI
3.16 ACCESS.BUS INTERFACE
3.17 MULTI-FUNCTION TIMER
3.21 POWER MANAGEMENT
3.22 DMA CONTROLLER
3.23 SERIAL DEBUG INTERFACE
3.24 DEVELOPMENT SUPPORT
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4.0 Signal Descriptions
CP3BT26 (LQFP-128)
CP3BT26 (LQFP-144)
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5.0 CPU Architecture
5.1 GENERAL-PURPOSE REGISTERS
5.2 DEDICATED ADDRESS REGISTERS
5.3 PROCESSOR STATUS REGISTER (PSR)
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5.4 CONFIGURATION REGISTER (CFG)
5.5 ADDRESSING MODES
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5.6 STACKS
5.7 INSTRUCTION SET
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6.0 Memory
6.1 OPERATING ENVIRONMENT
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6.2 BUS INTERFAC E UNIT (BIU)
6.3 BUS CYCLES
6.4 BIU CONTROL REGISTERS
CP3BT26
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6.5 WAIT AND HOLD STATES
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7.0 System Configuration Registers
7.1 MODULE CONFIGURATION REGISTER (MCFG)
7.2 MODULE STATUS REGISTER (MSTAT)
7.3 SOFTWARE RESET REGIS TER (SWRESET)
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8.0 Flash Memory
8.1 FLASH MEMORY PROTECTION
8.2 FLASH MEMORY ORGANIZATION
8.3 FLASH MEMORY OPERATIONS
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8.4 INFORMATION BLOCK WORDS
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8.5 FLASH MEMORY INTERFACE REGISTERS
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9.0 DMA Controller
9.1 CHANNEL ASSIGNMENT
9.2 TRANSFER TYPES
9.3 OPERATION MODES
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9.4 SOFTWARE DMA REQUEST
9.5 DEBUG MODE
9.6 DMA CONTROLLER REGISTER SET
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10.0 Interrupts
10.1 NON-MASKABLE INTERRUPTS
10.2 MASKABLE INTERRUPTS
10.3 INTERRUPT CONTROLLER REGISTERS
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10.4 MASKABLE INTERRUPT SOURCES
10.5 NESTED INTERRUPTS
11.0 Triple Clock and Reset
Figure 4. Triple Clock and Reset Module
11.1 EXTERNAL CRYSTAL NETWORK
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11.2 MAIN CLOCK
11.3 SLOW CLOCK
11.4 PLL CLOCK
11.5 SYSTEM CLOCK
11.6 AUXILIARY CLOCKS
11.7 POWER-ON RESET
11.8 EXTERNAL RESET
11.9 CLOCK AND RESET REGISTERS
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12.0 Power Management
12.1 ACTIVE MODE
12.2 POWER SAVE MODE
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12.3 IDLE MODE
12.4 HALT MODE
12.5 HARDWARE CLOCK CONTROL
12.6 POWER MANAGEMENT REGISTERS
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12.7 SWITCHING BETWEEN POWER MODES
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13.0 Multi-Input Wake-Up
13.1 MULTI-INPUT WAKE-UP REGISTERS
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13.2 PROGRAMMING PROCEDURES
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14.0 Input/Output Ports
14.1 PORT REGISTERS
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15.0 Bluetooth Controller
15.1 RF INTERFACE
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15.2 SERIAL INTERFACE
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15.3 LMX5251 POWER-UP SEQUENCE
15.4 LMX5252 POWER-UP SEQUENCE
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15.5 BLUETOOTH SLEEP MODE
15.6 BLUETOOTH GLOBAL REGISTERS
15.7 BLUETOOTH SEQUENCER RAM
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16.0 12-Bit Analog to Digital Converter
16.1 FUNCTIONAL DESCRIPTION
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16.2 TOUCHSCREEN INTERFACE
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16.3 ADC OPERATION IN POWER-SAVING MODES
16.4 FREEZE
16.5 ADC REGISTER SET
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17.0 Random Number Generator (RNG)
17.1 FREEZE
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17.2 RANDOM NUMBER GENERATOR REGISTER SET
18.0 USB Controller
18.1 FUNCTIONAL STATES
91
18.2 ENDPOINT OPERATION
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18.3 USB CONTROLLER REGISTERS
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18.4 TRANSCEIVER INTERFACE
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19.0 CAN Module
19.1 FUNCTIONAL DESCRIPTION
19.2 BASIC CAN CONCEPTS
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19.3 MESSAGE TRANSFER
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19.4 ACCEPTANCE FILTERING
19.5 RECEIVE STRUCTURE
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19.6 TRANSMIT STRUCTURE
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19.7 INTERRUPTS
19.8 TIME STAMP COUNTER
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19.9 MEMORY ORGANIZATION
19.10 CAN CONTROLLER REGISTERS
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19.11 SYSTEM START-UP AND MULTI-INPUT WAKE-U P
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19.12 USAGE HINT
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20.0 Advanced Audio Interface
20.1 AUDIO INTERFACE SIGNALS
20.2 AUDIO INTERFACE MODES
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20.3 BIT CLOCK GENERATION
20.4 FRAME CLOCK GENERATION
20.5 AUDIO INTERFACE OPERATION
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20.6 COMMUNICATION OPTIONS
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20.7 AUDIO INTERFACE REGISTERS
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21.0 CVSD/PCM Conversion Module
21.1 OPERATION
21.2 PCM CONVERSIONS
159
21.3 CVSD CONVERSION
21.4 PCM TO CVSD CONVERSION
21.5 CVSD TO PCM CONVERSION
21.6 INTERRUPT GENERATION
21.8 FREEZE
21.9 CVSD/PCM CONVERTER REGISTERS
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22.0 UART Modules
22.1 FUNCTIONAL OVERVIEW
22.2 UART OPERATION
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22.3 UART REGISTERS
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22.4 BAUD RATE CALCULATIONS
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23.0 Microwire/SPI Interface
23.1 MICROWIRE OPERATION
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23.2 MASTER MODE
Figure 88. Alternate Mode (SCIDL = 1)
Figure 85. Normal Mode (SCIDL = 0)
Figure 86. Normal Mode (SCIDL = 1)
23.3 SLAVE MODE
23.4 INTERRUPT GENERATION
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23.5 MICROWIRE INTERFACE REGISTERS
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24.0 ACCESS.bus Interface
24.1 ACB PROTOCOL OVERVIEW
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24.2 ACB FUNCTIONAL DESCRIPTION
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24.3 ACCESS.BUS INTERFACE REGISTERS
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24.4 USAGE HINTS
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25.0 Timing and Watchdog Module
25.1 TWM STRUCTURE
25.2 TIMER T0 OPERATION
193
25.3 WATCHDOG OPERATION
25.4 TWM REGISTERS
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25.5 WATCHDOG PROGRAMMING PROCEDURE
26.0 Multi-Function Timer
26.1 TIMER STRUCTURE
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26.2 TIMER OPERATING MODES
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26.3 TIMER INTERRUPTS
26.4 TIMER I/O FUNCTIONS
203
26.5 TIMER REGISTERS
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27.0 Versatile Timer Unit (VTU)
27.1 VTU FUNCTIONAL DESCRIPTION
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27.2 VTU REGISTERS
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28.0 Register Map
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29.0 Register Bit Fields
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30.0 Electrical Characteristics
30.2 DC ELECTRICAL CHARACTERISTICS
30.1 ABSOLUTE MAXIMUM RATINGS
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30.3 USB TRANSCEIVER ELECTRICAL CHARACTERISTICS
30.4 ADC ELECTRICAL CHARACTERISTICS
30.5 FLASH MEMORY ON-CHIP PROGRAMMING
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30.6 OUTPUT SIGNAL LEVELS
30.7 CLOCK AND RESET TIMING
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Figure 110. Clock Timing
Figure 113. Power-On Reset
Figure 111. NMI Signal Timing
Figure 112. Non-Power-On Reset
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30.8 UART TIMING
30.9 I/O PORT TIMING
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30.10 ADVANCED AUDIO INTERFACE (AAI) TIMING
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Figure 117. Transmit Timing, Short Frame Sync
Figure 119. Transmit Timing, Long Frame Sync
Figure 118. Receive Timing, Long Frame Sync
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30.11 MICROWIRE/SPI TIMING
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Figure 121. Microwire Transaction Timing, Normal Mode, SCIDL = 1
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Figure 122. Microwire Transaction Timing, Alternate Mode, SCIDL = 0
Figure 123. Microwire Transaction Timing, Alternate Mode, SCIDL = 1
30.12 ACCESS.BUS TIMING
Figure 125. ACB Signals (SDA and SCL) Timing
Figure 126. ACB Start and Stop Condition Timing
Figure 127. ACB Start Condition Timing
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Figure 128. ACB Data Timing
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30.13 USB PORT AC CHARACTERISTICS
30.14 MULTI-FUNCTION TIMER (MFT) TIMING
30.15 VERSATILE TIMING UNIT (VTU) TIMING
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30.16 EXTERNAL BUS TIMING
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Figure 131. Early Write Between Normal Read Cycles (No Wait States)
Figure 132. Late Write Between Normal Read Cycles (No Wait States)
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Figure 133. Consecutive Normal Read Cycles (Burst, No Wait States)
Figure 134. Normal Read Cycle (Wait Cycle Followed by Hold Cycle)
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Figure 135. Early Write Between Fast Read Cycles
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31.0 Pin Assignments
Figure 136. CP3BT26 in the LQFP-128 Package (Top View)
31.1 LQFP-128 PACKAGE
CP3BT26 (LQFP-128)
4, 10, 17, 43, 45, 49, 53, 67, 76, 79, 110, 117, 119, 124
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31.2 LQFP-144 PACKAGE
Figure 137. CP3BT26 in the LQFP-144 Package (Top View)
CP3BT26 (LQFP-144)
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32.0 Revision History
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CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces