National CP3BT26 19.10 CAN CONTROLLER REGISTERS

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CP3BT26

19.10 CAN CONTROLLER REGISTERS

Table51 lists the CAN module registers.

19.10.1 Buffer Status/Control Register (CNSTAT)

The buffer status (ST), the buffer priority (PRI), and the data

length code (DLC) are controlled by manipulating the con-

tents of the Buffer Status/Control Register (CNSTAT). The

CPU and CAN module have access to this register.

ST The Buffer Status field contains the status in-

formation of the buffer as shown in Table52.

This field can be modified by the CAN module.

The ST0 bits acts as a buffer busy indication.

When the BUSY bit is set, any write access to

the buffer is disabled with the exception of the

lower byte of the CNSTAT register. The CAN

module sets this bit if the buffer data is cur-

rently copied from the hidden buffer or if a

message is scheduled for transmission or is

currently transmitting. The CAN module al-

ways clears this bit on a status update.

Table 51 CAN Controller Registers

Name Address Description

CNSTAT See

Tabl e 50.

CAN Buffer Status/

Control Register

CGCR 0E F100h CAN Global

Configuration Register

CTIM 0E F102h CAN Timing Register

GMSKX 0E F104h Global Mask Register

GMSKB 0E F106h Global Mask Register

BMSKX 0E F108h Basic Mask Register

BMSKB 0E F10Ah Basic Mask Register

CIEN 0E F10Ch CAN Interrupt

Enable Register

CIPND 0E F10Eh CAN Interrupt

Pending Register

CICLR 0E F110h CAN Interrupt

Clear Register

CICEN 0E F112h CAN Interrupt Code

Enable Register

CSTPND 0E F114h CAN Status

Pending Register

CANEC 0E F116h CAN Error

Counter Register

CEDIAG 0E F118h CAN Error

Diagnostic Register

CTMR 0E F11Ah CAN Timer Register

15 12 11 8 7 4 3 0

DLC Reserved PRI ST

0

R/W

Contents

Main CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces PRELIMINARY CP3BT26 Reprogrammable Connectivity Processor with Bluetooth, USB, and CAN Interfaces 1.0 General Description Block Diagram CP3BT26 Table of Contents 6.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.0 System Configuration Registers . . . . . . . . . . . . . . . 29 8.0 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.0 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.0 Features 3.0 Device Overview 3.1 CR16C CPU CORE 3.2 MEMORY 3.3 INPUT/OUTPUT PORTS 3.4 BUS INTERFACE UNIT 3.7 BLUETOOTH LLC 3.8 USB 3.9 CAN INTERFACE 3.10 QUAD UART 3.11 ADVANCED AUDIO INTERFACE CP3BT26 3.14 RANDOM NUMBER GENERATOR 3.15 MICROWIRE/SPI 3.16 ACCESS.BUS INTERFACE 3.17 MULTI-FUNCTION TIMER 3.21 POWER MANAGEMENT 3.22 DMA CONTROLLER 3.23 SERIAL DEBUG INTERFACE 3.24 DEVELOPMENT SUPPORT www.national.com 8 4.0 Signal Descriptions CP3BT26 (LQFP-128) CP3BT26 (LQFP-144) Page Page Page Page Page Page 15 5.0 CPU Architecture 5.1 GENERAL-PURPOSE REGISTERS 5.2 DEDICATED ADDRESS REGISTERS 5.3 PROCESSOR STATUS REGISTER (PSR) 17 5.4 CONFIGURATION REGISTER (CFG) 5.5 ADDRESSING MODES 19 5.6 STACKS 5.7 INSTRUCTION SET Page Page Page Page 6.0 Memory 6.1 OPERATING ENVIRONMENT 25 6.2 BUS INTERFAC E UNIT (BIU) 6.3 BUS CYCLES 6.4 BIU CONTROL REGISTERS CP3BT26 27 6.5 WAIT AND HOLD STATES 29 7.0 System Configuration Registers 7.1 MODULE CONFIGURATION REGISTER (MCFG) 7.2 MODULE STATUS REGISTER (MSTAT) 7.3 SOFTWARE RESET REGIS TER (SWRESET) 31 8.0 Flash Memory 8.1 FLASH MEMORY PROTECTION 8.2 FLASH MEMORY ORGANIZATION 8.3 FLASH MEMORY OPERATIONS Page 8.4 INFORMATION BLOCK WORDS 35 8.5 FLASH MEMORY INTERFACE REGISTERS Page 37 Page Page Page 41 9.0 DMA Controller 9.1 CHANNEL ASSIGNMENT 9.2 TRANSFER TYPES 9.3 OPERATION MODES 43 9.4 SOFTWARE DMA REQUEST 9.5 DEBUG MODE 9.6 DMA CONTROLLER REGISTER SET Page 45 Page 47 10.0 Interrupts 10.1 NON-MASKABLE INTERRUPTS 10.2 MASKABLE INTERRUPTS 10.3 INTERRUPT CONTROLLER REGISTERS Page 49 10.4 MASKABLE INTERRUPT SOURCES 10.5 NESTED INTERRUPTS 11.0 Triple Clock and Reset Figure 4. Triple Clock and Reset Module 11.1 EXTERNAL CRYSTAL NETWORK 53 11.2 MAIN CLOCK 11.3 SLOW CLOCK 11.4 PLL CLOCK 11.5 SYSTEM CLOCK 11.6 AUXILIARY CLOCKS 11.7 POWER-ON RESET 11.8 EXTERNAL RESET 11.9 CLOCK AND RESET REGISTERS 55 12.0 Power Management 12.1 ACTIVE MODE 12.2 POWER SAVE MODE 57 12.3 IDLE MODE 12.4 HALT MODE 12.5 HARDWARE CLOCK CONTROL 12.6 POWER MANAGEMENT REGISTERS Page 59 12.7 SWITCHING BETWEEN POWER MODES Page 13.0 Multi-Input Wake-Up 13.1 MULTI-INPUT WAKE-UP REGISTERS 63 Page 65 13.2 PROGRAMMING PROCEDURES 67 14.0 Input/Output Ports 14.1 PORT REGISTERS Page 69 Page Page 15.0 Bluetooth Controller 15.1 RF INTERFACE 73 15.2 SERIAL INTERFACE Page Page 15.3 LMX5251 POWER-UP SEQUENCE 15.4 LMX5252 POWER-UP SEQUENCE 77 15.5 BLUETOOTH SLEEP MODE 15.6 BLUETOOTH GLOBAL REGISTERS 15.7 BLUETOOTH SEQUENCER RAM Page 79 16.0 12-Bit Analog to Digital Converter 16.1 FUNCTIONAL DESCRIPTION Page 81 16.2 TOUCHSCREEN INTERFACE Page 83 16.3 ADC OPERATION IN POWER-SAVING MODES 16.4 FREEZE 16.5 ADC REGISTER SET Page Page Page Page 17.0 Random Number Generator (RNG) 17.1 FREEZE 89 17.2 RANDOM NUMBER GENERATOR REGISTER SET 18.0 USB Controller 18.1 FUNCTIONAL STATES 91 18.2 ENDPOINT OPERATION Page 93 18.3 USB CONTROLLER REGISTERS Page Page Page Page Page Page Page Page Page Page Page Page Page 107 18.4 TRANSCEIVER INTERFACE 109 19.0 CAN Module 19.1 FUNCTIONAL DESCRIPTION 19.2 BASIC CAN CONCEPTS Page Page Page Page Page Page Page 19.3 MESSAGE TRANSFER 119 19.4 ACCEPTANCE FILTERING 19.5 RECEIVE STRUCTURE Page Page 123 19.6 TRANSMIT STRUCTURE Page 125 19.7 INTERRUPTS 19.8 TIME STAMP COUNTER 127 19.9 MEMORY ORGANIZATION 19.10 CAN CONTROLLER REGISTERS Page Page Page Page Page Page Page Page Page Page Page 19.11 SYSTEM START-UP AND MULTI-INPUT WAKE-U P Page 19.12 USAGE HINT 143 20.0 Advanced Audio Interface 20.1 AUDIO INTERFACE SIGNALS 20.2 AUDIO INTERFACE MODES Page Page 20.3 BIT CLOCK GENERATION 20.4 FRAME CLOCK GENERATION 20.5 AUDIO INTERFACE OPERATION Page 20.6 COMMUNICATION OPTIONS Page Page 151 20.7 AUDIO INTERFACE REGISTERS Page Page Page Page Page Page 21.0 CVSD/PCM Conversion Module 21.1 OPERATION 21.2 PCM CONVERSIONS 159 21.3 CVSD CONVERSION 21.4 PCM TO CVSD CONVERSION 21.5 CVSD TO PCM CONVERSION 21.6 INTERRUPT GENERATION 21.8 FREEZE 21.9 CVSD/PCM CONVERTER REGISTERS Page Page 163 22.0 UART Modules 22.1 FUNCTIONAL OVERVIEW 22.2 UART OPERATION Page Page Page Page 22.3 UART REGISTERS Page Page Page 22.4 BAUD RATE CALCULATIONS Page Page 175 23.0 Microwire/SPI Interface 23.1 MICROWIRE OPERATION Page 177 23.2 MASTER MODE Figure 88. Alternate Mode (SCIDL = 1) Figure 85. Normal Mode (SCIDL = 0) Figure 86. Normal Mode (SCIDL = 1) 23.3 SLAVE MODE 23.4 INTERRUPT GENERATION 179 23.5 MICROWIRE INTERFACE REGISTERS Page 181 24.0 ACCESS.bus Interface 24.1 ACB PROTOCOL OVERVIEW Page 183 24.2 ACB FUNCTIONAL DESCRIPTION Page 185 24.3 ACCESS.BUS INTERFACE REGISTERS Page Page Page 189 24.4 USAGE HINTS www.national.com 190 Page 25.0 Timing and Watchdog Module 25.1 TWM STRUCTURE 25.2 TIMER T0 OPERATION 193 25.3 WATCHDOG OPERATION 25.4 TWM REGISTERS Page 195 25.5 WATCHDOG PROGRAMMING PROCEDURE 26.0 Multi-Function Timer 26.1 TIMER STRUCTURE 197 26.2 TIMER OPERATING MODES Page Page Page Page 26.3 TIMER INTERRUPTS 26.4 TIMER I/O FUNCTIONS 203 26.5 TIMER REGISTERS Page Page 27.0 Versatile Timer Unit (VTU) 27.1 VTU FUNCTIONAL DESCRIPTION Page Page Page 27.2 VTU REGISTERS Page Page Page 28.0 Register Map Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 29.0 Register Bit Fields Page Page Page Page Page Page Page Page Page Page Page Page 243 30.0 Electrical Characteristics 30.2 DC ELECTRICAL CHARACTERISTICS 30.1 ABSOLUTE MAXIMUM RATINGS Page 245 30.3 USB TRANSCEIVER ELECTRICAL CHARACTERISTICS 30.4 ADC ELECTRICAL CHARACTERISTICS 30.5 FLASH MEMORY ON-CHIP PROGRAMMING 247 30.6 OUTPUT SIGNAL LEVELS 30.7 CLOCK AND RESET TIMING www.national.com 248 Figure 110. Clock Timing Figure 113. Power-On Reset Figure 111. NMI Signal Timing Figure 112. Non-Power-On Reset 249 30.8 UART TIMING 30.9 I/O PORT TIMING 251 30.10 ADVANCED AUDIO INTERFACE (AAI) TIMING www.national.com 252 Figure 117. Transmit Timing, Short Frame Sync Figure 119. Transmit Timing, Long Frame Sync Figure 118. Receive Timing, Long Frame Sync 253 30.11 MICROWIRE/SPI TIMING Page Figure 121. Microwire Transaction Timing, Normal Mode, SCIDL = 1 www.national.com 256 Figure 122. Microwire Transaction Timing, Alternate Mode, SCIDL = 0 Figure 123. Microwire Transaction Timing, Alternate Mode, SCIDL = 1 30.12 ACCESS.BUS TIMING Figure 125. ACB Signals (SDA and SCL) Timing Figure 126. ACB Start and Stop Condition Timing Figure 127. ACB Start Condition Timing www.national.com 260 Figure 128. ACB Data Timing 261 30.13 USB PORT AC CHARACTERISTICS 30.14 MULTI-FUNCTION TIMER (MFT) TIMING 30.15 VERSATILE TIMING UNIT (VTU) TIMING 263 30.16 EXTERNAL BUS TIMING www.national.com 264 Figure 131. Early Write Between Normal Read Cycles (No Wait States) Figure 132. Late Write Between Normal Read Cycles (No Wait States) www.national.com 266 Figure 133. Consecutive Normal Read Cycles (Burst, No Wait States) Figure 134. Normal Read Cycle (Wait Cycle Followed by Hold Cycle) www.national.com 268 Figure 135. Early Write Between Fast Read Cycles 269 31.0 Pin Assignments Figure 136. CP3BT26 in the LQFP-128 Package (Top View) 31.1 LQFP-128 PACKAGE CP3BT26 (LQFP-128) 4, 10, 17, 43, 45, 49, 53, 67, 76, 79, 110, 117, 119, 124 Page Page www.national.com 272 31.2 LQFP-144 PACKAGE Figure 137. CP3BT26 in the LQFP-144 Package (Top View) CP3BT26 (LQFP-144) Page Page Page 32.0 Revision History Page CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces