National CP3BT26 manual Uart Timing, Uart Output Signals

30.8UART TIMING

						Table 85		UART Signals
Symbol	Figure		Description						Reference					Min (ns)		Max (ns)
							UART Input Signals
tIs	114	Input setup time						Before Rising Edge (RE)								-
		RXD (asynchronous mode)						on CLK
tIh	114	Input hold time						After RE on CLK								-
		RXD (asynchronous mode)
						UART Output Signals
tCOv1	114	TXD output valid (all signals with						After RE on CLK							-
		propagation delay from CLK RE)
tTXD	114	TXD output valid						After RE on CLK							-	40
		1	2	1	2	1		2	1	2	1	2	1		2
		CLK
				tCOv1					tCOv1
		TXD

tlS

RXD

tlH

DS098

Figure 114. UART Asynchronous Mode Timing

CP3BT26

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