National CP3BT26 manual Static Zone 1 Configuration Register SZCFG1, WBR RBE Hold Wait Ipst

IPRE	The Preliminary Idle bit controls whether an
	idle cycle is inserted prior to the current bus
	cycle, when the new bus cycle accesses a dif-
	ferent zone. No idle cycles are required for on-
	chip accesses.
	0	– No idle cycle (recommended).
	1	– Idle cycle inserted.

6.4.4Static Zone 1 Configuration Register (SZCFG1)

The SZCFG1 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL1 output signal.

At reset, the register is initialized to 069Fh. The register for- mat is shown below.

7	6	5	4	3	2	0
BW	WBR	RBE	HOLD			WAIT

IPST	The Post Idle bit controls whether an idle cycle
	follows the current bus cycle, when the next
	bus cycle accesses a different zone.
	0	– No idle cycle.
	1	– Idle cycle inserted.
IPRE	The Preliminary Idle bit controls whether an
	idle cycle is inserted prior to the current bus
	cycle, when the new bus cycle accesses a dif-
	ferent zone.
	0	– No idle cycle.
	1	– Idle cycle inserted.

6.4.5Static Zone 2 Configuration Register (SZCFG2)

The SZCFG2 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL2 output signal.

At reset, the register is initialized to 069Fh. The register for- mat is shown below.

CP3BT26

15	12	11	10	9	8	7		6	5	4	3	2	0
							BW	WBR	RBE	HOLD			WAIT
Reserved		FRE	IPRE	IPST	Res.

WAIT	The Memory Wait field specifies the number
	of TIW (internal wait state) clock cycles added
	for each memory access, ranging from 000b
	for no additional TIW wait cycles to 111b for
	seven additional TIW wait cycles. These bits
	are ignored if the SZCFG1.FRE bit is set.
HOLD	The Memory Hold field specifies the number
	of Thold clock cycles used for each memory
	access, ranging from 00b for no Thold cycles
	to 11b for three Thold clock cycles. These bits
	are ignored if the SZCFG1.FRE bit is set.
RBE	The Read Burst Enable enables burst cycles
	on 16-bit reads from 8-bit bus width regions of
	the address space. This bit is ignored when
	the SZCFG1.FRE bit is set or the
	SZCFG1.BW is clear.
	0	– Burst read disabled.
	1	– Burst read enabled.
WBR	The Wait on Burst Read bit controls if a wait
	state is added on burst read transaction. This
	bit is ignored, when SZCFG1.FRE bit is set or
	when SZCFG1.RBE is clear.
	0	– No TBW on burst read cycles.
	1	– One TBW on burst read cycles.
BW	The Bus Width bit controls the bus width of the
	zone.
	0	– 8-bit bus width.
	1	– 16-bit bus width.
FRE	The Fast Read Enable bit controls whether
	fast read bus cycles are used. A fast read op-
	eration takes one clock cycle. A normal read
	operation takes at least two clock cycles.
	0	– Normal read cycles.
	1	– Fast read cycles.

15	12	11	10	9	8
	Reserved	FRE	IPRE	IPST	Res.
WAIT	The Memory Wait field specifies the number
	of TIW (internal wait state) clock cycles added
	for each memory access, ranging from 000b
	for no additional TIW wait cycles to 111b for
	seven additional TIW wait cycles. These bits
	are ignored if the SZCFG2.FRE bit is set.
HOLD	The Memory Hold field specifies the number
	of Thold clock cycles used for each memory
	access, ranging from 00b for no Thold cycles
	to 11b for three Thold clock cycles. These bits
	are ignored if the SZCFG2.FRE bit is set.
RBE	The Read Burst Enable enables burst cycles
	on 16-bit reads from 8-bit bus width regions of
	the address space. This bit is ignored when
	the SZCFG2.FRE bit is set or the
	SZCFG2.BW is clear.
	0 – Burst read disabled.
	1 – Burst read enabled.
WBR	The Wait on Burst Read bit controls if a wait
	state is added on burst read transaction. This
	bit is ignored, when SZCFG2.FRE bit is set or
	when SZCFG2.RBE is clear.
	0 – No TBW on burst read cycles.
	1 – One TBW on burst read cycles.
BW	The Bus Width bit controls the bus width of the
	zone.
	0 – 8-bit bus width.
	1 – 16-bit bus width.

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