Tgscl, ACB Control Register 1 ACBCTL1, Start | National CP3BT26

GCMTCH	The Global Call Match bit is set in slave mode
	when the ACBCTL1.GCMEN bit is set and the
	address byte (the first byte transferred after a
	Start Condition) is 00h. It is cleared by a Start
	Condition or repeated Start and Stop Condi-
	tion (including illegal Start or Stop Condition).
	0 – No global call match occurred.
	1 – Global call match occurred.
TSDA	The Test SDA bit samples the state of the SDA
	signal. This bit can be used while recovering
	from an error condition in which the SDA sig-
	nal is constantly pulled low by a slave that
	went out of sync. This bit is a read-only bit.
	Data written to it is ignored.
TGSCL	The Toggle SCL bit enables toggling the SCL
	signal during error recovery. When the SDA
	signal is low, writing 1 to this bit drives the SCL
	signal high for one cycle. Writing 1 to TGSCL
	when the SDA signal is high is ignored. The bit
	is cleared when the clock toggle is completed.
	0 – Writing 0 has no effect.
	1 – Writing 1 toggles the SDA signal high for
	one cycle.

24.3.4ACB Control Register 1 (ACBCTL1)

The ACBCTL1 register is a byte-wide, read/write register that configures and controls the ACB module. At reset and while the module is disabled (ACBCTL2.ENABLE = 0), the ACBCTL1 register is cleared.

7	6		5	4	3		2	1	0
STASTRE	NMINTE	GCMEN		ACK	Res.	INTEN		STOP	START

START	The Start bit is set to generate a Start Condi-
	tion on the ACCESS.bus. The START bit is
	cleared when the Start Condition is sent, or
	upon		detection		of		a	Bus	Error
	(ACBST.BER = 1). This bit should be set only
	when in Master mode, or when requesting
	Master mode. If this device is not the active
	master of the bus (ACBST.MASTER = 0), set-
	ting the START bit generates a Start
	Con0dition as soon as the ACCESS.bus is
	free (ACBCST.BB = 0). An address send se-
	quence should then be performed. If this de-
	vice is the active master of the bus
	(ACBST.MASTER = 1), when the START bit is
	set, a write to the ACBSDA register generates
	a Start Condition, then the ACBSDA data is
	transmitted as the slave’s address and the re-
	quested transfer direction. This case is a re-
	peated Start Condition. It may be used to
	switch the direction of the data flow between
	the master and the slave, or to choose anoth-
	er slave device without using a Stop Condition
	in between.
	0 – Writing 0 has no effect.
	1 – Writing 1 generates a Start condition.
STOP	The Stop bit in master mode generates a Stop
	Condition that completes or aborts the current
	message transfer. This bit clears itself after
	the Stop condition is issued.

0 – Writing 0 has no effect.

1 – Writing 1 generates a Stop condition.

CP3BT26

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Image 187

National CP3BT26 manual Tgscl, ACB Control Register 1 ACBCTL1, Start, Stop

Contents

National Semiconductor Corporation Block DiagramGeneral Description MAY Table of Contents Features Device Overview Advanced Audio Interface Bluetooth LLCCan Interface Quad Uart Versatile Timer Unit MICROWIRE/SPIACCESS.BUS Interface MULTI-FUNCTION Timer Development Support Power ManagementDMA Controller Serial Debug Interface LQFP-144 Signal DescriptionsCP3BT26 LQFP-128 X1CKO ResetX1CKI Bbclk Name Pins Primary Function Alternate Alternate Function PG6 PG4Sdat PG5 X1CKI CTS PE4 SelioWR0 WR1 SLE GENERAL-PURPOSE Registers CPU ArchitectureDedicated Address Registers No carry or borrow occurred Carry or borrow occurred Processor Status Register PSRInterrupt Base Register Intbase 12 11 Reserved Is held in the Intbase register, which is not Configuration Register CFGWhen the IDT has 16-bit entries, and all ex Mode for the CR16B large model. Addb R1, R2 Addressing ModesLoadw 12R5, R6 Instruction SET Stacks Instruction Set Summary Mnemonic Operands Description LPR AshudLshd Tbit Popret RetxPush POP Wait StormpEiwait NOP Operating Environment MemoryIN/A Empty BUS Interface Unit BIUBUS Cycles BIU Control Registers Static Zone 0 Configuration Register SZCFG0 2 I/O Zone Configuration Register Iocfg Static Zone 2 Configuration Register SZCFG2 Static Zone 1 Configuration Register SZCFG1WBR RBE Hold Wait Ipst RAM Memory Access to PeripheralsWait and Hold States Flash Program/Data Memory Module Configuration Register Mcfg System Configuration RegistersSystem Configuration Registers Name Address Description Module Status Register Mstat Software Reset Register Swreset Flash Memory Protection Flash MemoryFlash Memory Organization Flash Memory Operations Main Block Write Main Block Page EraseMain Block Module Erase Information Block Module Erase Information Block Words BootArea Empty Ispe CPU Reset BehaviorBoot Area Start-Up Operation Flash Memory Interface Registers FMIBDR/FSMIBDR Flash Memory 0 Write Enable Register FM0WER/FSM0WERFlash Memory 1 Write Enable Register FM1WER Flash Memory Information Block Data Register Flash Memory Control Register Fmctrl Flash Data Memory 0 Write Enable Register FSM0WERFsmctrl Fsmpsr FsmstatFMSTART/FSMSTART Flash Memory End Time Reload Register FMEND/FSMEND Flash Memory Auto-Read Register 0 FMAR0/ FSMAR0 FMRCV/FSMRCV FSMAR1Flash Memory Auto-Read Register 2 FMAR2/ FSMAR2 DMA Channel Assignment Peripheral Trans Register Action DMA ControllerChannel Assignment Transfer Types Operation Modes Software DMA Request Debug ModeDMA Controller Register SET Device B Address Register ADRBn Device a Address Counter Register ADCAnDevice a Address Register ADRAn Device B Address Counter Register ADCBn DMA Control Register DMACNTLn Block Length Register BLTRn VLD Chac OVR DMA Status Register DmastatVLD Interrupt Controller Registers InterruptsNON-MASKABLE Interrupts Maskable Interrupts External NMI Trap Control and Status Register Exnmi Interrupt Vector Register IvctNon-Maskable Interrupt Status Register Nmistat Interrupt Status Register 2 ISTAT2 Interrupt Enable and Mask Register 1 IENAM1Interrupt Enable and Mask Register 2 IENAM2 Interrupt Status Register 1 ISTAT1 IRQ Number Description Maskable Interrupt SourcesNested Interrupts Maskable Interrupts Assignment IRQ Number Description Triple Clock and Reset Module Triple Clock and Reset Capacitor C1, C2 Capacitance External Crystal NetworkCrystal Resonance Frequency Type Min. Q factor Main ClockSlow Clock PLL Clock System Clock POWER-ON ResetExternal Reset Clock and Reset Registers MODE20 Module Activity Summary Power Mode Clock Power ManagementActive Mode Power Save Mode Power Management Control Register Pmmcr Idle Mode Power Management RegistersHalt Mode Power Management Registers Name Address Description Hccm DHCHcch OHC OMC OLC Active Mode to Power Save ModeOHC Wake-Up Transition to Active Mode Entering Idle ModeEntering Halt Mode Software-Controlled Transition to Active Mode Multi-Input Wake-Up Multi-Input Wake-Up Module Block Diagram Multi-Input Wake-Up Registers Name Address Description MULTI-INPUT WAKE-UP RegistersMiwu Sources Miwu Channel Wake-Up 1 Edge Detection Register WK1EDG Wake-Up Interrupt Enable Register WK0IENAWake-Up 1 Interrupt Enable Register WK1IENA Wake-Up Enable Register WK0ENA WK1ICTL1 WK1ICTL2 Wake-Up Interrupt Control RegisterWK0ICTL1 WK0ICTL2 Wake-Up 1 Interrupt Control Register Wake-Up 1 Pending Clear Register WK1PCL Wake-Up Pending Register WK0PNDWake-Up Pending Clear Register WK0PCL Wake-Up 1 Pending Register WK1PND Programming Procedures Port Registers Input/Output Ports Address Description Port Registers Port Direction Register PxDIR Port Alternate Function Register PxALTPort Data Input Register PxDIN Port Data Output Register PxDOUT Port Pin PxALTS = Port High Drive Strength Register PxHDRVPort Alternate Function Select Register PxALTS Alternate Function Select OPEN-DRAIN Operation Rfdata Bluetooth ControllerRF Interface X1CKI/BBCLK Sdat Serial InterfaceRfce Sclk Serial Interface Write Timing Read Operation Write Operation First part of read cycle driven by CP3BT26. Address is 0Ah Bit, and register address for a read cycle. In the second 15.4 LMX5252 POWER-UP Sequence 15.3 LMX5251 POWER-UP Sequence Bluetooth Global Registers Bluetooth Sleep ModeBluetooth Sequencer RAM Bluetooth Shared Data RAM Functional Description 16.0 12-Bit Analog to Digital ConverterData Path Pen-Down Detector OperationADC Clock Generation ADC Voltage References Touchscreen Interface Touchscreen Driver Configuration RYP Measuring Pen ForceRX2 RY2 ADC Registers Name Address Description ADC Operation in POWER-SAVING ModesFreeze ADC Register SET Touchcfg ADC0/TSX+ ADC1/TSY+ ADC2/TSX ADC3/TSY Muxcfg Nrefcfg PrefcfgClkdiv ADC Conversion Control Register Adccntrl ADC Start Conversion Delay Register AdcscdlyADC Start Conversion Register Adcstart Sign ADC Result Register AdcresltAdcresult Adcoflw Random Number Generator RNG RNG Module Block Diagram Random Number Generator Register SET Functional States USB Controller TX Fifo RX Fifo Endpoint Operation Transmit Endpoint Fifo Operation TXFIFO1, TXFIFO2, TXFIFO3 Bidirectional Control Endpoint FIFO0 Operation Receive Endpoint Fifo Operation RXFIFO1, RXFIFO2, RXFIFO3 USB Controller RegistersUSB Controller Registers Name Address Description Main Control Register Mcntrl NFS Node Functional State Register NfsrNFS USB Functional States Main Mask Register Mamsk Main Event Register MaevAlternate Event Register Altev Transmit Event Register Txev Alternate Mask Register AltmskTransmit Mask Register Txmsk Receive Mask Register Rxmsk Receive Event Register Rxev NAK Event Register NakevNAK Mask Register Nakmsk Frame Number High Byte Register FNH Fifo Warning Event Register FwevFifo Warning Mask Register Fwmsk Dsrc DMA Event Register Dmaev DMA Count Register Dmacnt DMA Error Register DmaerrDMA Mask Register Dmamsk Mirror Register MIR Endpoint Control 0 Register EPC0 Transmit Command 0 Register TXC0Transmit Status 0 Register TXS0 Transmit Data 0 Register TXD0 Receive Command 0 Register RXC0Receive Status 0 Register RXS0 Endpoint Control Register n EPCn Receive Data 0 Register RXD0Transmit Status Register n TXSn RFF Transmit Command Register n TXCnTfwl Last Bytes Remaining in Fifo Transmit Fifo Warning LimitReceive Status Register n RXSn Tfwl Rfwl Receive Command Register n RXCn Receive Data Register n RXDTransceiver Interface Receive Fifo Warning Limit Can Module Basic can Concepts Can Block Diagram Arbitration Field Can Frame TypesCan Frame Fields Start of Frame SOF ACK Field Data Length Code DLCData Field Cyclic Redundancy Check CRC Data Field Remote FrameCyclic Redundancy Check Field CRC Error Frame Overload Frame Error Frame Acknowledgment Error Stuff ErrorForm Error Bit CRC Error Error Counters Error ActiveError Warning Error Passive Bit Timing Bit Time LogicCan Bit Time Synchronization CKI Message Transfer From the can bus Gmask and BMASK. shows Acceptance FilteringExample 1 Acceptance of a Single Identifier Two 32-bit masks are used to filter unwanted messages 120 Receive Structure Rxbusy Receive ProcedureReceive Timing Writing to Buffer Status Code During 122 Buffer Read Routine Bufflock Enabled Transmit Scheduling Transmit StructureTransmit Priority PRI Txpri TX Buffer States Interrupts IRQ IST3 IST2 IST1 IST0 Time Stamp Counter Message Buffer Map Address Register CPU Access to can Registers/MemoryMemory Organization Message Buffer Organization Can Controller Registers Name Address Description Can Controller RegistersBuffer Status/Control Register Cnstat ST3 DIR ST2 ST1 ST0 Busy Buffer Status Section of the Cnstat RegisterBuffer Status Standard Frame with 8 Data Bytes Address Buffer Register Data Length CodingDLC Storage of Standard Messages Cnstat DLC Extended Messages with 8 Data Bytes Address Buffer RegisterPRI SRR Extended Remote Frame Address Buffer Register Frame is received, the contents of these registers will beContents of these registers are ignored. If a remote Storage of Remote Messages Can Global Configuration Register Cgcr Dress, as shown in Figure Listen Only bit can be used to configureWhen the Ignore Acknowledge bit is set, When the Loopback bit is set, all messages SJW Xrtr TSEG1TSEG2 RTR IDE BM170 Can Interrupt Enable Register CienBasic Mask Register BMSKB/BMSKX Basic Mask BM2818 IRQ EFID30 Can Error Counter Register CanecCan Error Diagnostic Register Cediag Error Field Identifier External Connection Can Timer Register CtmrExternal can Pins Signal Name Type Description System START-UP and MULTI-INPUT WAKE-UP Remote Frames Minimum Clock Frequency Requirements Baud RateBit Time Logic Calculation Examples Acceptance Filter Considerations Usage Hint Advanced Audio Interface Audio Interface SignalsAudio Interface Modes Normal Mode Synchronous ModeDMA Support 145 Audio Interface Operation Clock ConfigurationFrame Clock Generation BIT Clock Generation Receive TransmitDMA Operation Fifo Operation Communication Options Frame Sync SignalData Word Length Short and Long Frame Sync Pulses Audio Control Data Loopback Mode IOM-2 Mode150 Audio Interface Registers Freeze ModeAudio Interface Registers Name Address Description Audio Transmit DMA Register n ATDRn Audio Receive Fifo Register ArfrAudio Transmit Fifo Register Atfr Audio Receive DMA Register n ARDRn FSL Audio Global Configuration Register AgcrSlots per Mode Frame SCS Txeip Audio Interrupt Status and Control Register AiscrTxeip Txip Rxeip Rxip Txeie Txie Rxeie Rxie Txeic Txic Rxeic Rxic Rxie Rxdsa Bit Slots Enabled For DMA Rxsa Bit Slots EnabledAudio Receive Status and Control Register Arscr Txdsa Bit Slots Enabled For DMA Txsa Bit Slots EnabledAudio Transmit Status and Control Register Atscr DMA Request Condition Audio Clock Control Register AccrAudio DMA Control Register Admacr RMD Operation CVSD/PCM Conversion ModulePCM Conversions Interrupt Generation Cvsd ConversionPCM to Cvsd Conversion Cvsd to PCM Conversion CVSD/PCM Converter Registers Linearout Cvsd Status Register Cvstat Functional Overview Uart ModulesUart Operation Uart Asynchronous Communication Uart Block Diagram Frame Format Selection Diagnostic Mode Prescaler Factor Prescaler Factors Parity Generation and Detection Break Generation and Detection Uart Registers Name Address Description Uart Registers Uart Frame Select Register UnFRS Uart Baud Rate Divisor UnBAUDUart Receive Data Buffer UnRBUF Uart Transmit Data Buffer UnTBUF Uart Status Register UnSTAT Uart Mode Select Register 1 UnMDSL1 Oversampling Rate Uart Interrupt Control Register UnICTRLUart Oversample Rate Register UnOVR UOVSR30 Oversampling Rate Sample Position Uart Mode Select Register 2 UnMDSL2Baud Rate Calculations Uart Sample Position Register UnSPOS 173 174 Shifting Microwire/SPI InterfaceMicrowire Operation Microwire Interface Clocking Modes Writing Normal Mode Scidl = Master Mode Microwire Interrupt Trigger Condition Status Enable Bit Slave ModeMWCTRL1 Mwen Microwire Interface Registers OVR RBF BSY Microwire Status Register MwstatSCM Scdv Start and Stop ACCESS.bus InterfaceACB Protocol Overview Data Transactions Addressing Transfer Formats Acknowledge CycleArbitration on the Bus ACB Functional Description Slave Error Detections Master Error DetectionsBus Idle Error Recovery Slave Mode ACCESS.BUS Interface Registers ACB Control Status Register Acbcst Stop TgsclACB Control Register 1 ACBCTL1 Start ACB Control Register 3 ACBCTL3 ACB Control Register 2 ACBCTL2 Saen Usage HintsACB Own Address Register 1 ACBADDR1 Saen Addr 190 Avoiding Bus Error During Write Transaction 191 Timing and Watchdog Module Timer T0 OperationTWM Structure Register Locking Power Save Mode OperationWatchdog Operation TWM Registers T0IN Mdiv Watchdog Count Register Wdcnt Watchdog Programming ProcedureWatchdog Service Data Match Register Wdsdm TWMT0 Control and Status Register T0CSR 196 Multi-Function TimerTimer Structure Clock Source Block Counter Clock Source Select Timer Operating ModesPulse Accumulate Mode Limitations in Low-Power Modes 198 Mode 1 Processor-Independent PWM Dual-Input Capture Mode Mode 2 Dual Input Capture 200 Mode 3 Dual Independent Timer/Counter Input Capture Plus Timer Mode Mode 4 Input Capture Plus Timer Tben Timer InterruptsTimer I/O Functions Taen Timer Registers Reload/Capture a Register Tcra Timer Mode Control Register TctrlReload/Capture B Register Tcrb Timer Interrupt Clear Register Ticlr Timer Interrupt Control Register Tictl VTU Functional Description Versatile Timer Unit VTU206 VTU PWM Generation Dual 8-bit PWM Mode 208 VTU 16-bit PWM Mode Dual 16-Bit Capture Mode ISE Mode operation VTU Dual 16-bit Capture Mode Low Power Mode VTU Registers Mode Control Register ModeVTU Registers Name Address Description Interrupt Control Register Intctl CxEDG Capture Counter Reset Interrupt Pending Register Intpnd Clock Prescaler Register 1 CLK1PSClock Prescaler Register 2 CLK2PS Period/Capture Register n PERCAPx Counter Register n COUNTxCNTx Duty Cycle/Capture Register n DTYCAPx Register Map Bluetooth LLC Registers USB Node Registers Register Name Size Address Access Value After Comments Type EPC4 EPC1TXC1 EPC2 Can Module Message Buffers DMA Controller Can Registers Bus Interface Unit Flash Program Memory Interface System ConfigurationFlash Data Memory Interface CVSD/PCM Converter Triple Clock + Reset General-Purpose I/O Ports Multi-Input Wake-Up Comments Type Register Name Size Address Interrupt Control Unit Advanced Audio Interface UART1 UART0 UART3 UART2 Multi-Function Timer ACCESS.busTiming and Watchdog ADC Versatile Timer Unit Word FF F284h RNGRngcst Rngd Register Bit Fields USB Fwmsk RXWARN31 Setup Toggle Rxlast Rcount RXC0IGN Ignout Rxen Setup EPC1 Nakev OUT Nakmsk Fwev RXWARN31 Control Status Can Dmac Memory Registers Flash System Configuration RegistersBIU TBI Register Flash Data Memory CLK3RES CVSD/PCM AAI PMM RegisterMIWU16 Gpio Registers Uart ICU Registers ACB Registers MWSPI16MFT16 VTU Rngdivh RngcstImsk Rngd TBD Electrical CharacteristicsSymbol Parameter Conditions Min Max Units Absolute Maximum Ratings IOOff DNL Symbol Parameter Conditions Min Typ Max UnitsINL LSB Flash Memory ON-CHIP Programming TRI-STATE Output Signal LevelsClock and Reset Timing Reset and NMI Input Signals Clock Timing NMI Signal Timing Uart Timing Uart Output Signals 30.9 I/O Port Timing Port Output Signals Advanced Audio Interface AAI Timing AAI Output Signals Receive Timing, Long Frame Sync Transmit Timing, Short Frame Sync Microwire/SPI Output Signals MICROWIRE/SPI TimingMicrowire/SPI Signals Symbol Description Reference Min ns Microwire/SPI Input Signals 254 Normal Mode After FE onMicrowire Data Out Valid Alternate Mode After RE On MSK Propagation Time 255 256 Microwire Transaction Timing, Alternate Mode, Scidl = 257 ACCESS.bus Output Signals ACCESS.BUS Timing 259 260 ACB Data Timing MULTI-FUNCTION Timer MFT Timing USB Port AC Characteristics 262 Versatile Timing Unit VTU TimingTIOx Input High Time Rising Edge RE on CLK TIOx Input Low Time RE on CLK External BUS Timing External Bus Output Signals 264 Early Write Between Normal Read Cycles No Wait States 265 266 Consecutive Normal Read Cycles Burst, No Wait States 267 268 Early Write Between Fast Read Cycles X1CKO X1CKI Pin AssignmentsLQFP-128 Package PWR SDA ADC0 TSX+ Reset TMSAvcc PWR Adgnd Advcc Uvcc X2CKI X2CKO ENV2 PF1 MDIDO/TIO2 PE0 RXD0 Gpio PE1 TXD0 PE2 RTS PE3 CTS PE4 CKX/TB PE5SRFS/NMI PF0 MSK/TIO1 272 LQFP-144 Package ADC7 Adcin SCL SDA ADC0 TSX+ADC4 MUXOUT0 ADC5 MUXOUT1 Pin Name Alternate Functions Pin Number Type A10 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13A12 A11 Revision History Revision HistoryDate Major Changes From Previous Version LQFP-128 Package LQFP-144 Package Physical Dimensions millimeters unless otherwise noted Life Support Policy Form when properly used in accordance with instructionsBanned Substance Compliance