National CP3BT26 manual Output Signal Levels, Clock and Reset Timing, Tri-State, RXD1, RXD2

30.6	OUTPUT SIGNAL LEVELS	The RESET and NMI input pins are active during the Power
All output signals are powered by the digital supply (VCC).		Save mode. In order to guarantee that the Power Save cur-
		rent not exceed 1 mA, these inputs must be driven to a volt-
Table 83 summarizes the states of the output signals during
		age lower than 0.5V or higher than VCC - 0.5V. An input
the reset state (when VCC power exists in the reset state)		voltage between 0.5V and (VCC - 0.5V) may result in power
and during the Power Save mode.		consumption exceeding 1 mA.

Table 83 Output Pins During Reset and Power-Save

Signals on a Pin	Reset State	Power Save Mode	Comments
	(with Vcc)
PB7:0	TRI-STATE	Previous state	I/O ports will maintain their values when
			entering power-save mode
PC7:0	TRI-STATE	Previous state
PE5:0	TRI-STATE	Previous state
PF7:0	TRI-STATE	Previous state
PG7:0	TRI-STATE	Previous state
PH7:0	TRI-STATE	Previous state
PJ7:0	TRI-STATE	Previous state

30.7CLOCK AND RESET TIMING

Table 84 Clock and Reset Signals

Symbol	Figure			Description					Reference	Min (ns)	Max (ns)
						Clock Input Signals
tX1p	110		X1 period				Rising Edge (RE) on X1 to			83.33	83.33
							next RE on X1
tX1h	110		X1 high time, external clock				At 2V level (Both Edges)			(0.5 Tclk) - 5
tX1l	110		X1 low time, external clock				At 0.8V level (Both Edges)			(0.5 Tclk) - 5
tX2p	110		X2 perioda				RE on X2 to next RE on X2			10,000
tX2h	110		X2 high time, external clock				At 2V level (both edges)			(0.5 Tclk) - 500
tX2l	110		X2 low time, external clock				At 0.8V level (both edges)			(0.5 Tclk) - 500
tIH	111		Input hold time			RXD1, RXD2)	After RE on CLK			0
					(NMI,
						Reset and NMI Input Signals
tIW							NMI	Falling Edge (FE) to
	111	NMI Pulse Width								20
							RE
tRST	112			Pulse Width					FE to RE	100
			RESET				RESET
tR	112		Vcc Rise Time				0.1 Vcc to 0.9 Vcc

a.Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed this given limit.

CP3BT26

247 www.national.com