National CP3BT26 manual Transmit Command Register n TXCn, Tfwl, Last, Rff

CP3BT26

ACK_STAT The Acknowledge Status bit is valid when the TX_DONE bit is set. The meaning of the ACK_STAT bit differs depending on whether ISO or non-ISO operation is used (as selected by the ISO bit in the EPCn register).

„Non-Isochronous mode—This bit indi- cates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set when an ACK is received; otherwise, it is clear.

„Isochronous mode—This bit is set if a frame number LSB match occurs (see Section 18.3.33), and data was sent in re- sponse to an IN token. Otherwise, this bit

is cleared, the FIFO is flushed, and TX_DONE is set.

The ACK_STAT bit is cleared when this regis- ter is read.

TX_URUN The Transmit FIFO Underrun indicates wheth- er the transmit FIFO became empty during a transmission, and no new data was written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared when this register is read.

0 – No transmit FIFO underrun event oc- curred.

1 – Transmit FIFO underrun event occurred.

18.3.33 Transmit Command Register n (TXCn)

Each of the transmit endpoints (1, 3, and 5) has a Transmit Command Register, TXCn. These registers provide read/ write access from the CPU bus. After reset the registers are clear.

7	6		5	4	3	2	1	0
IGN_ISOMSK		TFWL		RFF	FLUSH	TOGGLE	LAST	TX_EN
TX_EN	The Transmission Enable bit enables data
	transmission from the FIFO. It is cleared by
	hardware after transmitting a single packet or
	after a STALL handshake in response to an IN

token. It must be set by software to start pack- et transmission.

0 – Transmission disabled.

1 – Transmission enabled.

LAST	The Last Byte bit indicates whether the entire
	packet has been written into the FIFO. This is
	used especially for streaming data to the FIFO
	while the actual transmission occurs. If the
	LAST bit is not set and the transmit FIFO be-
	comes empty during a transmission, a stuff er-
	ror followed by an EOP is forced on the bus.
	Zero length packets are indicated by setting
	this bit without writing any data to the FIFO.
	The transmit state machine transmits the pay-
	load data, CRC16, and the EOP signal before
	clearing this bit.
	0 – Last byte of the packet has not been writ-
	ten to the FIFO.
	1 – Last byte of the packet has been written to
	the FIFO.
TOGGLE	The function of the Toggle bit differs depend-
	ing on whether ISO or non-ISO operation is
	used (as selected by the ISO bit in the EPCn
	register).
	„ Non-Isochronous mode—The TOGGLE
	bit specifies the PID used when transmit-
	ting the packet. A value of 0 causes a
	DATA0 PID to be generated, while a value
	of 1 causes a DATA1 PID to be generated.
	„ Isochronous mode—The TOGGLE bit
	and the LSB of the frame counter (FNL0)
	act as a mask for the TX_EN bit to allow
	pre-queueing of packets to specific frame
	numbers. (I.e. transmission is enabled
	only if bit 0 in the FNL register is set to
	TOGGLE.) If an IN token is not received
	while this condition is true, the contents of
	the FIFO are flushed with the next SOF. If
	the endpoint is set to ISO, data is always
	transferred with a DATA0 PID.
	This bit is not altered by hardware.
FLUSH	Writing 1 to the Flush bit flushes all data from
	the corresponding transmit FIFO, resets the
	endpoint to Idle state, and clears both the
	FIFO read and write pointers. If the MAC is
	currently using the FIFO to transmit, data is
	flushed after the transmission is complete. Af-
	ter data flushing, this bit is cleared by hard-
	ware.
	0 – Writing 0 has no effect.
	1 – Writing 1 flushes the FIFO.
RFF	The Refill FIFO bit is used to repeat a trans-
	mission for which no ACK was received. Set-
	ting the LAST bit to 1 automatically saves the
	Transmit Read Pointer (TXRP) to a buffer.
	When the RFF bit is set, the buffered TXRP is
	reloaded into the TXRP. This allows software
	to repeat the last transaction if no ACK was re-
	ceived from the host. If the MAC is currently
	using the FIFO to transmit, TXRP is reloaded
	only after the transmission is complete. After
	reload, this bit is cleared by hardware.
	0 – No action.
	1 – Reload the saved TXRP.

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