National CP3BT26 manual Alternate Mask Register Altmsk, Transmit Event Register Txev

SD3	The Suspend Detect 3 ms bit is set after 3 ms
	of IDLE have been detected on the upstream
	port, indicating that the device should be sus-
	pended. The suspend occurs under software
	control by writing the suspend value to the
	Node Functional State (NFSR) register. This
	bit is cleared when the register is read.
	0 – No 3 ms in IDLE has been detected.
	1 – 3 ms in IDLE has been detected.
SD5	The Suspend Detect 5 ms bit is set after 5 ms
	of IDLE have been detected on the upstream
	port, indicating that this device is permitted to
	perform a remote wake-up operation. The re-
	sume may be initiated under software control
	by writing the resume value to the NFSR reg-
	ister. This bit is cleared when the register is
	read.
	0 – No 5 ms in IDLE has been detected.
	1 – 5 ms in IDLE has been detected.
RESET	The Reset bit is set when 2.5 ∝s of SEO have
	been detected on the upstream port. In re-
	sponse, the functional state should be reset
	(NFS in the NFSR register is set to RESET),
	where it must remain for at least 100 ∝s. The
	functional state can then return to Operational
	state. This bit is cleared when the register is
	read.
	0 – No 2.5 ∝s in SEO have been detected.
	1 – 2.5 ∝s in SEO have been detected.
RESUME	The Resume bit indicates whether resume
	signalling has been detected on the USB
	when the device is in Suspend state (NFS in
	the NFSR register is set to SUSPEND), and a
	non-IDLE signal is present on the USB, indi-
	cating that this device should begin its wake-
	up sequence and enter Operational state. Re-
	sume signalling can only be detected when
	the 48 MHz PLL clock is enabled to the USB
	controller. This bit is cleared when the register
	is read.
	0 – No resume signalling detected.
	1 – Resume signalling detected.

18.3.6Alternate Mask Register (ALTMSK)

A set bit in the ALTMSK register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting MAEV.ALT bit is disabled. The ALTMSK register is clear af- ter reset. It provides read/write access from the CPU bus.

18.3.7Transmit Event Register (TXEV)

The TXEV register reports the current status of the FIFOs, used by the three Transmit Endpoints. The TXEV register is clear after reset. It provides read-only access.

7	4	3	0
TXUDRRN			TXFIFO
TXFIFO	The Transmit FIFO n bits are copies of the
	TX_DONE bits from the corresponding Trans-
	mit Status registers (TXSn). A bit is set when
	the IN transaction for the corresponding trans-
	mit endpoint n has been completed. These
	bits are cleared when the corresponding
	TXSn register is read.
TXUDRRN	The Transmit Underrun n bits are copies of the
	respective TX_URUN		bits from the corre-

sponding Transmit Status registers (TXSn). Whenever any of the Transmit FIFOs under- flows, the respective TXUDRRN bit is set. These bits are cleared when the correspond- ing Transmit Status register is read.

Note: Since Endpoint 0 implements a store and forward principle, an underrun condition for FIFO0 cannot occur. This results in the TXUDRRN0 bit always being read as 0.

18.3.8Transmit Mask Register (TXMSK)

The TXMSK register is used to select the bits of the TXEV registers, which causes the TX_EV bit in the MAEV register to be set. When a bit is set and the corresponding bit in the TXEV register is set, the TX_EV bit in the MAEV register is set. When clear, the corresponding bit in the TXEV register does not cause TX_EV to be set. The TXMSK register pro- vides read/write access. It is clear after reset.

7	4	3	0
	TXUDRRN		TXFIFO

CP3BT26

7	6	5	4	3	2	1	0
RESUME	RESET	SD5	SD3	EOP	DMA	Reserved

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