National CP3BT26 manual Fifo Warning Event Register Fwev, Frame Number High Byte Register FNH

18.3.13 FIFO Warning Event Register (FWEV)

The FWEV register signals whether a receive or transmit FIFO has reached its warning limit. It reports the status for all FIFOs, except for the Endpoint 0 FIFO, as no warning limit can be specified for this FIFO. The FWEV register pro- vides read-only access from the CPU bus. It is clear after re- set.

18.3.15 Frame Number High Byte Register (FNH)

The FNH register contains the three most significant bits (MSB) of the current frame counter as well as status and control bits for the frame counter. This register is loaded with C0h after reset. It provides access from the CPU bus as de- scribed below.

CP3BT26

						7		6	5	4	3	2	0
7	5	4	3	1	0
							MF	UL	RFC	Reserved			FN10:8
RXWARN3:1		Res.		TXWARN3:1	Res.

TXWARN3:1	The Transmit Warning n bits are set when the
	respective transmit endpoint FIFO reaches
	the warning limit, as specified by the TFWL
	bits of the respective TXCn register, and
	transmission from the respective endpoint is
	enabled. These bits are cleared when the
	warning condition is cleared by either writing
	new data to the FIFO when the FIFO is
	flushed, or when transmission is done, as in-
	dicated by the TX_DONE bit in the TXSn reg-
	ister.
RXWARN3:1	The Receive Warning n bits are set when the
	respective receive endpoint FIFO reaches the
	warning limit, as specified by the RFWL bits of
	the respective EPCx register. These bits are
	cleared when the warning condition is cleared
	by either reading data from the FIFO or when
	the FIFO is flushed.

18.3.14 FIFO Warning Mask Register (FWMSK)

The FWMSK register selects which FWEV bits are reported in the MAEV register. A set FWMSK bit with the correspond- ing bit in the FWEV register set, causes the WARN bit in the MAEV register to be set. When clear, the corresponding bit in the FWEV register does not cause WARN to be set. The FWMSK register provides read/write access. This register is clear after reset.

7	5	4	3	1	0
RXWARN3:1		Res.		TXWARN3:1	Res.

FN10:8	The Frame Number field holds the three most
	significant bits (MSB) of the current frame
	number, received in the last SOF packet. If a
	valid frame number is not received within
	12060 bit times (Frame Length Maximum, FL-
	MAX, with tolerance) of the previous change,
	the frame number is incremented artificially. If
	two successive frames are missed or are in-
	correct, the current FN is frozen and loaded
	with the next frame number from a valid SOF
	packet. If the frame number low byte was read
	by software before reading the FNH register,
	software actually reads the contents of a buff-
	er register which holds the value of the three
	frame number bits of this register when the
	low byte was read. Therefore, the correct se-
	quence to read the frame number is: FNL,
	FNH. Read operations to the FNH register,
	without first reading the Frame Number Low
	Byte (FNL) register directly, read the actual
	value of the three MSBs of the frame number.
	The FN bits provide read-only access. On re-
	set, the FN bits are cleared.
RFC	The Reset Frame Count bit is used to reset
	the frame number to 000h. This bit always
	reads as 0. Due to the synchronization ele-
	ments the frame counter reset actually occurs
	a maximum of 3 USB clock cycles (12 MHz)
	plus 2.5 CPU clock cycles after the write to the
	RFC bit.
	0 – Writing 0 has no effect.
	1 – Writing 1 resets the frame counter.
UL	The Unlock Flag bit indicates that at least two
	frames were received without an expected
	frame number, or that no valid SOF was re-
	ceived within 12060 bit times. If this bit is set,
	the frame number from the next valid SOF
	packet is loaded in FN. The UL bit provides
	read-only access. After reset, this bit is set.
	This bit is set by the hardware and is cleared
	by reading the FNH register.
	0 – No condition indicated.
	1 – At least two frames were received without
	an expected frame number, or no valid
	SOF was received within 12060 bit times.

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