National CP3BT26 manual Clock Prescaler Register 1 CLK1PS, Interrupt Pending Register Intpnd

CP3BT26

IxCEN	The Timer x Interrupt C Enable bit controls in-
	terrupt requests triggered on the correspond-
	ing IxCPD bit being set. The associated
	IxCPD bit will be updated regardless of the
	value of the IxCEN bit.
	0 – Disable system interrupt request for the
	IxCPD pending bit.
	1 – Enable system interrupt request for the Ix-
	CPD pending bit.
IxDEN	Timer x Interrupt D Enable bit controls inter-
	rupt requests triggered on the corresponding
	IxDPD bit being set. The associated IxDPD bit
	will be updated regardless of the value of the
	IxDEN bit.
	0 – Disable system interrupt request for the
	IxDPD pending bit.
	1 – Enable system interrupt request for the
	IxDPD pending bit.

IxDPD	The Timer x Interrupt D Pending bit indicates
	that an interrupt condition for the related timer
	subsystem has occurred. Table 80 on page
	209 lists the hardware condition which causes
	this bit to be set.
	0	– No interrupt pending.
	1	– Timer interrupt condition occurred.

27.2.6Clock Prescaler Register 1 (CLK1PS)

The CLK1PS register is a word-wide read/write register. The register is split into two 8-bit fields called C1PRSC and C2PRSC. Each field holds the 8-bit clock prescaler com- pare value for timer subsystems 1 and 2 respectively. The register is cleared at reset.

15	8	7	0
	C2PRSC		C1PRSC

27.2.5Interrupt Pending Register (INTPND)

The INTPND register is a word-wide read/write register which contains all 16 interrupt pending bits. There are four interrupt pending bits called IxAPD through IxDPD for each timer subsystem. Each interrupt pending bit is set by a hard- ware event and can be cleared if software writes a 1 to the bit position. The value will remain unchanged if a 0 is written to the bit position. All interrupt pending bits are cleared (0) upon reset.

7	6	5	4		3		2	1		0
I2DPD	I2CPD	I2BPD	I2APD	I1DPD		I1CPD		I1BPD	I1APD
15	14	13	12		11		10	9		8
I4DPD	I4CPD	I4BPD	I4APD	I3DPD		I3CPD		I3BPD	I3APD
IxAPD	The Timer x Interrupt A Pending bit indicates
	that an interrupt condition for the related timer
	subsystem has occurred. Table 80 on page
	209 lists the hardware condition which causes
	this bit to be set.
	0	– No interrupt pending.
	1	– Timer interrupt condition occurred.
IxBPD	The Timer x Interrupt B Pending bit indicates
	that an interrupt condition for the related timer
	subsystem has occurred. Table 80 on page
	209 lists the hardware condition which causes
	this bit to be set.
	0	– No interrupt pending.
	1	– Timer interrupt condition occurred.
IxCPD	The Timer x Interrupt C Pending bit indicates
	that an interrupt condition for the related timer
	subsystem has occurred. Table 80 on page
	209 lists the hardware condition which causes
	this bit to be set.
	0	– No interrupt pending.
	1	– Timer interrupt condition occurred.

C1PRSC	The Clock Prescaler 1 Compare Value field
	holds the 8-bit prescaler value for timer sub-
	system 1. The counter of timer subsystem is
	incremented each time when the clock pres-
	caler compare value matches the value of the
	clock prescaler counter. The division ratio is
	equal to (C1PRSC + 1). For example, 00h is a
	ratio of 1, and FFh is a ratio of 256.
C2PRSC	The Clock Prescaler 2 Compare Value field
	holds the 8-bit prescaler value for timer sub-
	system 2. The counter of timer subsystem is
	incremented each time when the clock pres-
	caler compare value matches the value of the
	clock prescaler counter. The division ratio is
	equal to (C2PRSC + 1).

27.2.7Clock Prescaler Register 2 (CLK2PS)

The Clock Prescaler Register 2 (CLK2PS) is a word-wide read/write register. The register is split into two 8-bit fields called C3PRSC and C4PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 3 and 4 respectively. The register is cleared at reset.

15	8	7	0
	C4PRSC		C3PRSC
C3PRSC	The Clock Prescaler 3 Compare Value field
	holds the 8-bit prescaler value for timer sub-
	system 3. The counter of timer subsystem is
	incremented each time when the clock pres-
	caler compare value matches the value of the
	clock prescaler counter. The division ratio is
	equal to (C3PRSC + 1).
C4PRSC	The Clock Prescaler 4 Compare Value field
	holds the 8-bit prescaler value for timer sub-
	system 4. The counter of timer subsystem is

incremented each time when the clock pres- caler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C4PRSC + 1).

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