Master Mode, Normal Mode Scidl = | National CP3BT26 specification

23.2MASTER MODE

In Master mode, the MSK pin is an output for the shift clock, MSK. When data is written to the MWDAT register, eight or sixteen MSK clocks, depending on the mode selected, are

MSK

Shift

Out

generated to shift the 8 or 16 bits of data, and then MSK goes idle again. The MSK idle state can be either high or low, depending on the SCIDL bit.

End of Transfer

CP3BT26

Data Out	MSB	MSB - 1	MSB - 2	Bit 1
	Sample
	Point
Data In	MSB	MSB - 1	MSB - 2	Bit 1

Figure 85. Normal Mode (SCIDL = 0)

MSK
	Shift
	Out
Data Out	MSB	MSB - 1	MSB - 2	Bit 1
	Sample
	Point
Data In	MSB	MSB - 1	MSB - 2	Bit 1

Figure 86. Normal Mode (SCIDL = 1)

MSK
	Shift
	Out
Data Out	MSB	MSB - 1	MSB - 2	Bit 1
	Sample
	Point
Data In	MSB	MSB - 1	MSB - 2	Bit 1

Figure 87. Alternate Mode (SCIDL = 0)

MSK
		Shift
		Out
Data Out	MSB	MSB - 1	MSB - 2	Bit 1
	Sample
	Point
Data In	MSB	MSB - 1	MSB - 2	Bit 1

Figure 88. Alternate Mode (SCIDL = 1)

Bit 0

(LSB)

Bit 0

(LSB)

DS069

End of Transfer

Bit 0

(LSB)

Bit 0

(LSB)

DS070

End of Transfer

Bit 0

(LSB)

Bit 0

(LSB)

DS071

End of Transfer

Bit 0

(LSB)

Bit 0

(LSB)

DS072

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Image 177

National CP3BT26 manual Master Mode, Normal Mode Scidl =

Contents

General Description Block DiagramMAY National Semiconductor Corporation Table of Contents Features Device Overview Can Interface Bluetooth LLCQuad Uart Advanced Audio Interface ACCESS.BUS Interface MICROWIRE/SPIMULTI-FUNCTION Timer Versatile Timer Unit DMA Controller Power ManagementSerial Debug Interface Development Support CP3BT26 Signal DescriptionsLQFP-128 LQFP-144 X1CKI ResetBbclk X1CKO Name Pins Primary Function Alternate Alternate Function Sdat PG4PG5 PG6 X1CKI WR0 SelioWR1 CTS PE4 SLE CPU Architecture GENERAL-PURPOSE RegistersDedicated Address Registers Interrupt Base Register Intbase Processor Status Register PSR12 11 Reserved No carry or borrow occurred Carry or borrow occurred When the IDT has 16-bit entries, and all ex Configuration Register CFGMode for the CR16B large model. Is held in the Intbase register, which is not Addressing Modes Addb R1, R2Loadw 12R5, R6 Instruction SET Stacks Instruction Set Summary Mnemonic Operands Description Lshd AshudTbit LPR Push RetxPOP Popret Eiwait StormpNOP Wait Memory Operating EnvironmentIN/A BUS Cycles BUS Interface Unit BIUBIU Control Registers Empty Static Zone 0 Configuration Register SZCFG0 2 I/O Zone Configuration Register Iocfg Static Zone 1 Configuration Register SZCFG1 Static Zone 2 Configuration Register SZCFG2WBR RBE Hold Wait Ipst Wait and Hold States Access to PeripheralsFlash Program/Data Memory RAM Memory System Configuration Registers Module Configuration Register McfgSystem Configuration Registers Name Address Description Module Status Register Mstat Software Reset Register Swreset Flash Memory Flash Memory ProtectionFlash Memory Organization Flash Memory Operations Main Block Module Erase Main Block Page EraseInformation Block Module Erase Main Block Write Boot Information Block WordsArea Boot Area Start-Up Operation CPU Reset BehaviorFlash Memory Interface Registers Empty Ispe Flash Memory 1 Write Enable Register FM1WER Flash Memory 0 Write Enable Register FM0WER/FSM0WERFlash Memory Information Block Data Register FMIBDR/FSMIBDR Flash Data Memory 0 Write Enable Register FSM0WER Flash Memory Control Register FmctrlFsmctrl Fsmstat FsmpsrFMSTART/FSMSTART Flash Memory End Time Reload Register FMEND/FSMEND FMRCV/FSMRCV FSMAR1 Flash Memory Auto-Read Register 0 FMAR0/ FSMAR0Flash Memory Auto-Read Register 2 FMAR2/ FSMAR2 Channel Assignment DMA ControllerTransfer Types DMA Channel Assignment Peripheral Trans Register Action Operation Modes Debug Mode Software DMA RequestDMA Controller Register SET Device a Address Register ADRAn Device a Address Counter Register ADCAnDevice B Address Counter Register ADCBn Device B Address Register ADRBn DMA Control Register DMACNTLn Block Length Register BLTRn DMA Status Register Dmastat VLD Chac OVRVLD NON-MASKABLE Interrupts InterruptsMaskable Interrupts Interrupt Controller Registers Interrupt Vector Register Ivct External NMI Trap Control and Status Register ExnmiNon-Maskable Interrupt Status Register Nmistat Interrupt Enable and Mask Register 2 IENAM2 Interrupt Enable and Mask Register 1 IENAM1Interrupt Status Register 1 ISTAT1 Interrupt Status Register 2 ISTAT2 Nested Interrupts Maskable Interrupt SourcesMaskable Interrupts Assignment IRQ Number Description IRQ Number Description Triple Clock and Reset Module Triple Clock and Reset Crystal Resonance Frequency External Crystal NetworkType Capacitor C1, C2 Capacitance Slow Clock Main ClockPLL Clock Min. Q factor External Reset POWER-ON ResetClock and Reset Registers System Clock MODE20 Active Mode Power ManagementPower Save Mode Module Activity Summary Power Mode Clock Halt Mode Idle Mode Power Management RegistersPower Management Registers Name Address Description Power Management Control Register Pmmcr DHC HccmHcch Active Mode to Power Save Mode OHC OMC OLCOHC Entering Halt Mode Entering Idle ModeSoftware-Controlled Transition to Active Mode Wake-Up Transition to Active Mode Multi-Input Wake-Up Multi-Input Wake-Up Module Block Diagram Miwu Sources MULTI-INPUT WAKE-UP RegistersMiwu Channel Multi-Input Wake-Up Registers Name Address Description Wake-Up 1 Interrupt Enable Register WK1IENA Wake-Up Interrupt Enable Register WK0IENAWake-Up Enable Register WK0ENA Wake-Up 1 Edge Detection Register WK1EDG WK0ICTL1 WK0ICTL2 Wake-Up Interrupt Control RegisterWake-Up 1 Interrupt Control Register WK1ICTL1 WK1ICTL2 Wake-Up Pending Clear Register WK0PCL Wake-Up Pending Register WK0PNDWake-Up 1 Pending Register WK1PND Wake-Up 1 Pending Clear Register WK1PCL Programming Procedures Port Registers Input/Output Ports Address Description Port Registers Port Data Input Register PxDIN Port Alternate Function Register PxALTPort Data Output Register PxDOUT Port Direction Register PxDIR Port Alternate Function Select Register PxALTS Port High Drive Strength Register PxHDRVAlternate Function Select Port Pin PxALTS = OPEN-DRAIN Operation RF Interface Bluetooth ControllerX1CKI/BBCLK Rfdata Rfce Serial InterfaceSclk Sdat Serial Interface Write Timing Read Operation Write Operation First part of read cycle driven by CP3BT26. Address is 0Ah Bit, and register address for a read cycle. In the second 15.4 LMX5252 POWER-UP Sequence 15.3 LMX5251 POWER-UP Sequence Bluetooth Sleep Mode Bluetooth Global RegistersBluetooth Sequencer RAM Bluetooth Shared Data RAM 16.0 12-Bit Analog to Digital Converter Functional DescriptionData Path ADC Clock Generation OperationADC Voltage References Pen-Down Detector Touchscreen Interface Touchscreen Driver Configuration RX2 Measuring Pen ForceRY2 RYP Freeze ADC Operation in POWER-SAVING ModesADC Register SET ADC Registers Name Address Description Touchcfg ADC0/TSX+ ADC1/TSY+ ADC2/TSX ADC3/TSY Muxcfg Prefcfg NrefcfgClkdiv ADC Start Conversion Delay Register Adcscdly ADC Conversion Control Register AdccntrlADC Start Conversion Register Adcstart Adcresult ADC Result Register AdcresltAdcoflw Sign Random Number Generator RNG RNG Module Block Diagram Random Number Generator Register SET Functional States USB Controller TX Fifo RX Fifo Endpoint Operation Transmit Endpoint Fifo Operation TXFIFO1, TXFIFO2, TXFIFO3 Bidirectional Control Endpoint FIFO0 Operation USB Controller Registers Receive Endpoint Fifo Operation RXFIFO1, RXFIFO2, RXFIFO3USB Controller Registers Name Address Description Main Control Register Mcntrl NFS Node Functional State Register NfsrUSB Functional States NFS Main Event Register Maev Main Mask Register MamskAlternate Event Register Altev Alternate Mask Register Altmsk Transmit Event Register TxevTransmit Mask Register Txmsk Receive Event Register Rxev NAK Event Register Nakev Receive Mask Register RxmskNAK Mask Register Nakmsk Fifo Warning Event Register Fwev Frame Number High Byte Register FNHFifo Warning Mask Register Fwmsk Dsrc DMA Event Register Dmaev DMA Mask Register Dmamsk DMA Error Register DmaerrMirror Register MIR DMA Count Register Dmacnt Transmit Command 0 Register TXC0 Endpoint Control 0 Register EPC0Transmit Status 0 Register TXS0 Receive Command 0 Register RXC0 Transmit Data 0 Register TXD0Receive Status 0 Register RXS0 Receive Data 0 Register RXD0 Endpoint Control Register n EPCnTransmit Status Register n TXSn Tfwl Transmit Command Register n TXCnLast RFF Receive Status Register n RXSn Transmit Fifo Warning LimitTfwl Bytes Remaining in Fifo Transceiver Interface Receive Command Register n RXCn Receive Data Register n RXDReceive Fifo Warning Limit Rfwl Can Module Basic can Concepts Can Block Diagram Can Frame Fields Can Frame TypesStart of Frame SOF Arbitration Field Data Field Data Length Code DLCCyclic Redundancy Check CRC ACK Field Remote Frame Data FieldCyclic Redundancy Check Field CRC Error Frame Overload Frame Error Frame Form Error Stuff ErrorBit CRC Error Acknowledgment Error Error Warning Error ActiveError Passive Error Counters Can Bit Time Bit Time LogicSynchronization Bit Timing CKI Message Transfer Example 1 Acceptance of a Single Identifier Acceptance FilteringTwo 32-bit masks are used to filter unwanted messages From the can bus Gmask and BMASK. shows 120 Receive Structure Receive Timing Receive ProcedureWriting to Buffer Status Code During Rxbusy 122 Buffer Read Routine Bufflock Enabled Transmit Structure Transmit SchedulingTransmit Priority PRI Txpri TX Buffer States Interrupts IRQ IST3 IST2 IST1 IST0 Time Stamp Counter Memory Organization CPU Access to can Registers/MemoryMessage Buffer Organization Message Buffer Map Address Register Can Controller Registers Can Controller Registers Name Address DescriptionBuffer Status/Control Register Cnstat Buffer Status Section of the Cnstat Register ST3 DIR ST2 ST1 ST0 BusyBuffer Status DLC Data Length CodingStorage of Standard Messages Standard Frame with 8 Data Bytes Address Buffer Register Extended Messages with 8 Data Bytes Address Buffer Register Cnstat DLCPRI SRR Contents of these registers are ignored. If a remote Frame is received, the contents of these registers will beStorage of Remote Messages Extended Remote Frame Address Buffer Register Can Global Configuration Register Cgcr When the Ignore Acknowledge bit is set, Listen Only bit can be used to configureWhen the Loopback bit is set, all messages Dress, as shown in Figure SJW TSEG2 TSEG1RTR IDE Xrtr Basic Mask Register BMSKB/BMSKX Can Interrupt Enable Register CienBasic Mask BM2818 BM170 IRQ Can Error Diagnostic Register Cediag Can Error Counter Register CanecError Field Identifier EFID30 External can Pins Signal Name Type Description Can Timer Register CtmrSystem START-UP and MULTI-INPUT WAKE-UP External Connection Bit Time Logic Calculation Examples Minimum Clock Frequency Requirements Baud RateAcceptance Filter Considerations Remote Frames Usage Hint Audio Interface Signals Advanced Audio InterfaceAudio Interface Modes Synchronous Mode Normal ModeDMA Support 145 Frame Clock Generation Clock ConfigurationBIT Clock Generation Audio Interface Operation DMA Operation TransmitFifo Operation Receive Frame Sync Signal Communication OptionsData Word Length Short and Long Frame Sync Pulses Audio Control Data IOM-2 Mode Loopback Mode150 Freeze Mode Audio Interface RegistersAudio Interface Registers Name Address Description Audio Transmit Fifo Register Atfr Audio Receive Fifo Register ArfrAudio Receive DMA Register n ARDRn Audio Transmit DMA Register n ATDRn Slots per Mode Frame Audio Global Configuration Register AgcrSCS FSL Txeip Txip Rxeip Rxip Txeie Txie Rxeie Rxie Audio Interrupt Status and Control Register AiscrTxeic Txic Rxeic Rxic Rxie Txeip Rxsa Bit Slots Enabled Rxdsa Bit Slots Enabled For DMAAudio Receive Status and Control Register Arscr Txsa Bit Slots Enabled Txdsa Bit Slots Enabled For DMAAudio Transmit Status and Control Register Atscr Audio DMA Control Register Admacr Audio Clock Control Register AccrRMD DMA Request Condition CVSD/PCM Conversion Module OperationPCM Conversions PCM to Cvsd Conversion Cvsd ConversionCvsd to PCM Conversion Interrupt Generation CVSD/PCM Converter Registers Linearout Cvsd Status Register Cvstat Uart Modules Functional OverviewUart Operation Uart Asynchronous Communication Uart Block Diagram Frame Format Selection Diagnostic Mode Prescaler Factor Prescaler Factors Parity Generation and Detection Break Generation and Detection Uart Registers Name Address Description Uart Registers Uart Receive Data Buffer UnRBUF Uart Baud Rate Divisor UnBAUDUart Transmit Data Buffer UnTBUF Uart Frame Select Register UnFRS Uart Status Register UnSTAT Uart Mode Select Register 1 UnMDSL1 Uart Oversample Rate Register UnOVR Uart Interrupt Control Register UnICTRLUOVSR30 Oversampling Rate Baud Rate Calculations Uart Mode Select Register 2 UnMDSL2Uart Sample Position Register UnSPOS Oversampling Rate Sample Position 173 174 Microwire Operation Microwire/SPI InterfaceMicrowire Interface Shifting Clocking Modes Writing Normal Mode Scidl = Master Mode Slave Mode Microwire Interrupt Trigger Condition Status Enable BitMWCTRL1 Mwen Microwire Interface Registers SCM Microwire Status Register MwstatScdv OVR RBF BSY ACB Protocol Overview ACCESS.bus InterfaceData Transactions Start and Stop Acknowledge Cycle Addressing Transfer FormatsArbitration on the Bus ACB Functional Description Bus Idle Error Recovery Master Error DetectionsSlave Mode Slave Error Detections ACCESS.BUS Interface Registers ACB Control Status Register Acbcst ACB Control Register 1 ACBCTL1 TgsclStart Stop ACB Control Register 3 ACBCTL3 ACB Control Register 2 ACBCTL2 ACB Own Address Register 1 ACBADDR1 Usage HintsSaen Addr Saen 190 Avoiding Bus Error During Write Transaction 191 Timer T0 Operation Timing and Watchdog ModuleTWM Structure Watchdog Operation Power Save Mode OperationTWM Registers Register Locking T0IN Mdiv Watchdog Service Data Match Register Wdsdm Watchdog Programming ProcedureTWMT0 Control and Status Register T0CSR Watchdog Count Register Wdcnt Timer Structure Multi-Function TimerClock Source Block 196 Pulse Accumulate Mode Timer Operating ModesLimitations in Low-Power Modes Counter Clock Source Select 198 Mode 1 Processor-Independent PWM Dual-Input Capture Mode Mode 2 Dual Input Capture 200 Mode 3 Dual Independent Timer/Counter Input Capture Plus Timer Mode Mode 4 Input Capture Plus Timer Timer I/O Functions Timer InterruptsTaen Tben Timer Registers Timer Mode Control Register Tctrl Reload/Capture a Register TcraReload/Capture B Register Tcrb Timer Interrupt Clear Register Ticlr Timer Interrupt Control Register Tictl Versatile Timer Unit VTU VTU Functional Description206 VTU PWM Generation Dual 8-bit PWM Mode 208 VTU 16-bit PWM Mode Dual 16-Bit Capture Mode ISE Mode operation VTU Dual 16-bit Capture Mode Low Power Mode Mode Control Register Mode VTU RegistersVTU Registers Name Address Description Interrupt Control Register Intctl CxEDG Capture Counter Reset Clock Prescaler Register 1 CLK1PS Interrupt Pending Register IntpndClock Prescaler Register 2 CLK2PS CNTx Counter Register n COUNTxDuty Cycle/Capture Register n DTYCAPx Period/Capture Register n PERCAPx Register Map Bluetooth LLC Registers USB Node Registers Register Name Size Address Access Value After Comments Type TXC1 EPC1EPC2 EPC4 Can Module Message Buffers DMA Controller Can Registers Bus Interface Unit System Configuration Flash Program Memory InterfaceFlash Data Memory Interface CVSD/PCM Converter Triple Clock + Reset General-Purpose I/O Ports Multi-Input Wake-Up Comments Type Register Name Size Address Interrupt Control Unit Advanced Audio Interface UART1 UART0 UART3 UART2 ACCESS.bus Multi-Function TimerTiming and Watchdog ADC Versatile Timer Unit Rngcst RNGRngd Word FF F284h Register Bit Fields USB IGN Ignout Rxen Setup EPC1 Setup Toggle Rxlast Rcount RXC0Nakev OUT Nakmsk Fwev RXWARN31 Fwmsk RXWARN31 Control Status Can Dmac Memory Registers BIU System Configuration RegistersTBI Register Flash Flash Data Memory CLK3RES CVSD/PCM MIWU16 PMM RegisterGpio Registers AAI Uart ICU Registers MWSPI16 ACB RegistersMFT16 VTU Imsk RngcstRngd Rngdivh Symbol Parameter Conditions Min Max Units Electrical CharacteristicsAbsolute Maximum Ratings TBD IOOff INL Symbol Parameter Conditions Min Typ Max UnitsLSB DNL Flash Memory ON-CHIP Programming Clock and Reset Timing Output Signal LevelsReset and NMI Input Signals TRI-STATE Clock Timing NMI Signal Timing Uart Timing Uart Output Signals 30.9 I/O Port Timing Port Output Signals Advanced Audio Interface AAI Timing AAI Output Signals Receive Timing, Long Frame Sync Transmit Timing, Short Frame Sync Microwire/SPI Signals Symbol Description Reference Min ns MICROWIRE/SPI TimingMicrowire/SPI Input Signals Microwire/SPI Output Signals Microwire Data Out Valid Normal Mode After FE onAlternate Mode After RE On MSK Propagation Time 254 255 256 Microwire Transaction Timing, Alternate Mode, Scidl = 257 ACCESS.bus Output Signals ACCESS.BUS Timing 259 260 ACB Data Timing MULTI-FUNCTION Timer MFT Timing USB Port AC Characteristics TIOx Input High Time Rising Edge RE on CLK Versatile Timing Unit VTU TimingTIOx Input Low Time RE on CLK 262 External BUS Timing External Bus Output Signals 264 Early Write Between Normal Read Cycles No Wait States 265 266 Consecutive Normal Read Cycles Burst, No Wait States 267 268 Early Write Between Fast Read Cycles LQFP-128 Package Pin AssignmentsPWR X1CKO X1CKI Avcc PWR Adgnd Advcc Uvcc Reset TMSX2CKI X2CKO ENV2 SDA ADC0 TSX+ SRFS/NMI PE0 RXD0 Gpio PE1 TXD0 PE2 RTS PE3 CTS PE4 CKX/TB PE5PF0 MSK/TIO1 PF1 MDIDO/TIO2 272 LQFP-144 Package ADC4 MUXOUT0 SCL SDA ADC0 TSX+ADC5 MUXOUT1 ADC7 Adcin Pin Name Alternate Functions Pin Number Type A12 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13A11 A10 Revision History Revision HistoryDate Major Changes From Previous Version LQFP-128 Package LQFP-144 Package Physical Dimensions millimeters unless otherwise noted Form when properly used in accordance with instructions Life Support PolicyBanned Substance Compliance