National CP3BT26 manual Entering Idle Mode, Disabling the High-Frequency Clock, Entering Halt Mode

CP3BT26

12.7.2Entering Idle Mode

Entry into Idle mode is performed by writing a 1 to the PM- MCR.IDLE bit and then executing a WAIT instruction. The PMMCR.WBPSM bit must be set before the WAIT instruc- tion is executed. Idle mode can be entered only from the Ac- tive or Power Save mode.

12.7.3Disabling the High-Frequency Clock

When the low-frequency oscillator is used to generate the Slow Clock, power consumption can be reduced further in the Power Save or Idle mode by disabling the high-frequen- cy oscillator. This is accomplished by writing a 1 to the PM- MCR.DHC bit before executing the WAIT instruction that puts the device in the Power Save or Idle mode. The high- frequency clock is turned off only after the device enters the Power Save or Idle mode.

The CPU operates on the low-frequency clock in Power Save mode. It can turn off the high-frequency clock at any time by writing a 1 to the PMMCR.DHC bit. The high-fre- quency oscillator is always enabled in Active mode and al- ways disabled in Halt mode, without regard to the PMMCR.DHC bit setting.

Immediately after power-up and entry into Active mode, software must wait for the low-frequency clock to become stable before it can put the device in Power Save mode. It should monitor the PMMSR.OLC bit for this purpose. Once this bit is set, Slow Clock is stable and Power Save mode can be entered.

12.7.4Entering Halt Mode

Entry into Halt mode is accomplished by writing a 1 to the PMMCR.HALT bit and then executing a WAIT instruction. The PMMCR.WBPSM bit must be set before the WAIT in- struction is executed. Halt mode can be entered only from Active or Power Save mode.

12.7.5Software-Controlled Transition to Active Mode

A transition from Power Save mode to Active mode can be accomplished by either a software command or a hardware wake-up event. The software method is to write a 0 to the PMMCR.PSM bit. The value of the register bit changes only after the transition to the Active mode is completed.

If the high-frequency oscillator is disabled for Power Save operation, the oscillator must be enabled and allowed to sta- bilize before the transition to Active mode. To enable the high-frequency oscillator, software writes a 0 to the PM- MCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit, software must first monitor the PMMSR.OMC bit to deter- mine when the oscillator has stabilized.

12.7.6Wake-Up Transition to Active Mode

A hardware wake-up event switches the device directly from Power Save, Idle, or Halt mode to Active mode. Hardware wake-up events are:

„Non-Maskable Interrupt (NMI)

„Valid wake-up event on a Multi-Input Wake-Up channel

When a wake-up event occurs, the on-chip hardware per- forms the following steps:

1.Clears the PMMCR.DMC bit, which enables the high- frequency clock (if it was disabled).

2.Waits for the PMMSR.OMC bit to become set, which in- dicates that the high-frequency clock is operating and is stable.

3.Clears the PMMCR.DHC bit, which enables the PLL.

4.Waits for the PMMSR.OHC bit to become set.

5.Switches the device into Active mode.

12.7.7Power Mode Switching Protection

The Power Management Module has several mechanisms to protect the device from malfunctions caused by missing or unstable clock signals.

The PMMSR.OHC, PMMSR.OMC, and PMMSR.OLC bits indicate the current status of the PLL, high-frequency oscil- lator, and low-frequency oscillator, respectively. Software can check the appropriate bit before switching to a power mode that requires the clock. A set status bit indicates an operating, stable clock. A clear status bit indicates a clock that is disabled, not available, or not yet stable. (Except in the case of the PLL, which has a set status bit when dis- abled.)

During a power mode transition, if there is a request to switch to a mode with a clear status bit, the switch is delayed until that bit is set by the hardware.

When the system is built without an external crystal network for the low-frequency clock, Main Clock is divided by a pres- caler factor to produce the low-frequency clock. In this situ- ation, Main Clock is disabled only in the Halt mode, and cannot be disabled for the Power Save or Idle mode.

Without an external crystal network for the low-frequency clock, the device comes out of Halt or Idle mode and enters Active mode with Main Clock driving Slow Clock.

Note: For correct operation in the absence of a low-fre- quency crystal, the X2CKI pin must be tied low (not left float- ing) so that the hardware can detect the absence of the crystal.

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