National CP3BT26 manual Advanced Audio Interface, Audio Interface Signals, Audio Interface Modes

20.0 Advanced Audio Interface

The Advanced Audio Interface (AAI) provides a serial syn- chronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asyn- chronously with respect to each other. Each path uses a 3- wire interface consisting of a bit clock, a frame synchroniza- tion signal, and a data signal.

The CPU interface can be either interrupt-driven or DMA. If the interface is configured for interrupt-driven I/O, data is buffered in the receive and transmit FIFOs. If the interface is configured for DMA, the data is buffered in registers.

The AAI is functionally similar to a MotorolaTM Synchronous Serial Interface (SSI). Compared to a standard SSI imple- mentation, the AAI interface does not support the so-called “On-demand Mode”. It also does not allow gating of the shift clocks, so the receive and transmit shift clocks are always active while the AAI is enabled. The AAI also does not sup- port 12- and 24-bit data word length or more than 4 slots (words) per frame. The reduction of supported modes is ac- ceptable, because the main purpose of the AAI is to connect to audio codecs, rather than to other processors (DSPs).

The implementation of a FIFO as a 16-word receive and transmit buffer is an additional feature, which simplifies communication and reduces interrupt load. Independent DMA is provided for each of the four supported audio chan- nels (slots). The AAI also provides special features and op- erating modes to simplify gain control in an external codec and to connect to an ISDN controller through an IOM-2 compatible interface.

20.1AUDIO INTERFACE SIGNALS

20.1.1Serial Transmit Data (STD)

The STD pin is used to transmit data from the serial transmit shift register (ATSR). The STD pin is an output when data is being transmitted and is in high-impedance mode when no data is being transmitted. The data on the STD pin changes on the positive edge of the transmit shift clock (SCK). The STD pin goes into high-impedance mode on the negative edge of SCK of the last bit of the data word to be transmit- ted, assuming no other data word follows immediately. If an- other data word follows immediately, the STD pin remains active rather than going to the high-impedance mode.

20.1.2Serial Transmit Clock (SCK)

The SCK pin is a bidirectional signal that provides the serial shift clock. In asynchronous mode, this clock is used only by the transmitter to shift out data on the positive edge. The se- rial shift clock may be generated internally or it may be pro- vided by an external clock source. In synchronous mode, the SCK pin is used by both the transmitter and the receiver. Data is shifted out from the STD pin on the positive edge, and data is sampled on the SRD pin on the negative edge.

20.1.3Serial Transmit Frame Sync (SFS)

The SFS pin is a bidirectional signal which provides frame synchronization. In asynchronous mode, this signal is used as frame sync only by the transmitter. In synchronous mode, this signal is used as frame sync by both the transmitter and receiver. The frame sync signal may be generated internally, or it may be provided by an external source.

20.1.4Serial Receive Data (SRD)

The SRD pin is used as an input when data is shifted into the Audio Receive Shift Register (ARSR). In asynchronous mode, data on the SRD pin is sampled on the negative edge of the serial receive shift clock (SRCLK). In synchronous mode, data on the SRD pin is sampled on the negative edge of the serial shift clock (SCK). The data is shifted into ARSR with the most significant bit (MSB) first.

20.1.5Serial Receive Clock (SRCLK)

The SRCLK pin is a bidirectional signal that provides the re- ceive serial shift clock in asynchronous mode. In this mode, data is sampled on the negative edge of SRCLK. The SR- CLK signal may be generated internally or it may be provid- ed by an external clock source. In synchronous mode, the SCK pin is used as shift clock for both the receiver and transmitter, so the SRCLK pin is available for use as a gen- eral-purpose port pin or an auxiliary frame sync signal to ac- cess multiple slave devices (e.g. codecs) within a network (see Network mode).

20.1.6Serial Receive Frame Sync (SRFS)

The SRFS pin is a bidirectional signal that provides frame synchronization for the receiver in asynchronous mode. The frame sync signal may be generated internally, or it may be provided by an external source. In synchronous mode, the SFS signal is used as the frame sync signal for both the transmitter and receiver, so the SRFS pin is available for use as a general-purpose port pin or an auxiliary frame sync sig- nal to access multiple slave devices (e.g. codecs) within a network (see Network mode).

20.2AUDIO INTERFACE MODES

There are two clocking modes: asynchronous mode and synchronous mode. These modes differ in the source and timing of the clock signals used to transfer data. When the AAI is generating the bit shift clock and frame sync signals internally, synchronous mode must be used.

There are two framing modes: normal mode and network mode. In normal mode, one word is transferred per frame. In network mode, up to four words are transferred per frame. A word may be 8 or 16 bits. The part of the frame which car- ries a word is called a slot. Network mode supports multiple external devices sharing the interface, in which each device is assigned its own slot. Separate frame sync signals are provided, so that each device is triggered to send or receive its data during its assigned slot.

20.2.1Asynchronous Mode

In asynchronous mode, the receive and transmit paths of the audio interface operate independently, with each path using its own bit clock and frame sync signal. Independent clocks for receive and transmit are only used when the bit clock and frame sync signal are supplied externally. If the bit clock and frame sync signals are generated internally, both paths derive their clocks from the same set of clock prescal- ers.

CP3BT26

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