10.3.4 Interrupt Enable and Mask Register 0 (IENAM0)

 

10.3.7 Interrupt Status Register 0 (ISTAT0)

 

 

The IENAM0 register is a word-wide read/write register

 

The ISTAT0 register is a word-wide read-only register. It in-

which holds bits that individually enable and disable the

 

dicates which maskable interrupt inputs to the ICU are ac-

maskable interrupt sources IRQ1 through IRQ15. The reg-

 

tive. These bits are not affected by the state of the

ister is initialized to FFFFh at reset.

 

 

 

corresponding IENA bits.

 

 

15

1

0

15

1

0

 

 

 

 

 

 

 

IENA

 

Res.

 

IST

 

Res.

 

 

 

 

 

 

 

CP3BT26

IENA

Each Interrupt Enable bit enables or disables

 

the corresponding interrupt request IRQ1

 

through IRQ15, for example IENA15 controls

 

IRQ15. Because IRQ0 is not used, IENA0 is

 

ignored.

 

0

Interrupt is disabled.

 

1

Interrupt is enabled.

10.3.5Interrupt Enable and Mask Register 1 (IENAM1)

The IENAM1 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ16 through IRQ31. The reg- ister is initialized to FFFFh at reset.

IST

The Interrupt Status bits indicate if a

 

maskable interrupt source is signalling an in-

 

terrupt request. IST15:1 correspond to IRQ15

 

to IRQ1 respectively. Because the IRQ0 inter-

 

rupt is not used, bit 0 always reads back 0.

 

0

Interrupt is not active.

 

1

Interrupt is active.

10.3.8Interrupt Status Register 1 (ISTAT1)

The ISTAT1 register is a word-wide read-only register. It in- dicates which maskable interrupt inputs into the ICU are ac- tive. These bits are not affected by the state of the corresponding IENA bits.

15

0

15

0

 

IENA

 

 

IST

 

 

 

 

 

IENA

Each Interrupt Enable bit enables or disables

 

the corresponding interrupt request IRQ16

 

through IRQ31, for example IENA31 controls

 

IRQ31.

 

0

Interrupt is disabled.

 

1

Interrupt is enabled.

10.3.6Interrupt Enable and Mask Register 2 (IENAM2)

The IENAM2 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ32 through IRQ47. The reg- ister is initialized to FFFFh at reset.

IST

The Interrupt Status bits indicate if a

 

maskable interrupt source is signalling an in-

 

terrupt request. IST31:16 correspond to

 

IRQ31 to IRQ16, respectively.

 

0

Interrupt is not active.

 

1

Interrupt is active.

10.3.9Interrupt Status Register 2 (ISTAT2)

The ISTAT2 register is a word-wide read-only register. It in- dicates which maskable interrupt inputs into the ICU are ac- tive. These bits are not affected by the state of the corresponding IENA bits.

15

 

0

15

 

0

 

 

IENA

 

 

 

IST

 

 

 

 

 

IENA

Each Interrupt Enable bit enables or disables

 

IST

The Interrupt Status bits indicate if a

 

the corresponding interrupt request IRQ32

 

 

maskable interrupt source is signalling an in-

 

through IRQ47, for example IENA47 controls

 

 

terrupt request. IST47:32 correspond to

 

IRQ47.

 

 

IRQ47 to IRQ32, respectively.

 

0

Interrupt is disabled.

 

 

0

Interrupt is not active.

 

1

Interrupt is enabled.

 

 

1

Interrupt is active.

49

www.national.com

Page 49
Image 49
National CP3BT26 manual Interrupt Enable and Mask Register 1 IENAM1, Interrupt Status Register 1 ISTAT1