ACCESS.BUS Timing, ACCESS.bus Output Signals | National CP3BT26

CP3BT26

30.12ACCESS.BUS TIMING

			Table 89	ACCESS.bus Signals

Symbol		Figure	Description		Reference	Min (ns)			Max (ns)

			ACCESS.bus Input Signals

tBUFi		126	Bus free time between Stop and Start			tSCLhigho			-
tBUFi		126	Condition			tSCLhigho			-
tCSTOsi		126	SCL setup time		Before Stop Condition	(8 × tCLK) - tSCLri			-
tCSTRhi		126	SCL hold time		After Start Condition	(8 × tCLK) - tSCLri			-
tCSTRsi		126	SCL setup time		Before Start Condition	(8 × tCLK) - tSCLri			-
tDHCsi		127	Data High setup time		Before SCL Rising Edge	2 × tCLK			-
tDHCsi		127	Data High setup time		(RE)	2 × tCLK			-
tDLCsi		126	Data Low setup time		Before SCL RE	2 × tCLK			-
tSCLfi		125	SCL signal rise time				-		300
tSCLri		125	SCL signal fall time				-		1000
tSCLlowi		128	SCL low time		After SCL Falling Edge	16 × tCLK			-
tSCLlowi		128	SCL low time		(FE)	16 × tCLK			-
tSCLhighi		128	SCL high time		After SCL RE	16 × tCLK			-
tSDAri		125	SDA signal rise time				-		1000
tSDAfl		125	SDA signal fall time				-		300
tSDAhi		128	SDA hold time		After SCL FE		0		-
tSDAsi		128	SDA setup time		Before SCL RE	2 × tCLK			-
			ACCESS.bus Output Signals

tBUFo		126	Bus free time between Stop and Start			tSCLhigho
			Condition

tCSTOso		126	SCL setup time		Before Stop Condition	tSCLhigho
tCSTRho		126	SCL hold time		After Start Condition	tSCLhigho
tCSTRso		127	SCL setup time		Before Start Condition	tSCLhigho
tDHCso		127	Data High setup time		Before SCL R.E.	tSCLhigho -tSDAro
tDLCso		126	Data Low setup time		Before SCL R.E.	tSCLhigho -tSDAfo
tSCLfo		125	SCL signal Fall time						300c
tSCLro		125	SCL signal Rise time						- d
t	SCLlowo	128	SCL low time		After SCL F.E.	(K × t		) -1e
	SCLlowo						CLK
t	SCLhigh	128	SCL high time		After SCL R.E.	(K × t		) -1e
	SCLhigh						CLK
o
tSDAfo		125	SDA signal Fall time						300
tSDAro		125	SDA signal Rise time						-
tSDAho		128	SDA hold time		After SCL F.E.	(7 × tCLK) - tSCLfo
tSDAvo		128	SDA valid time		After SCL F.E.				(7 × tCLK) + tRD

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National CP3BT26 manual ACCESS.BUS Timing, ACCESS.bus Output Signals

Contents

MAY Block DiagramGeneral Description National Semiconductor Corporation Table of Contents Features Device Overview Quad Uart Bluetooth LLCCan Interface Advanced Audio Interface MULTI-FUNCTION Timer MICROWIRE/SPIACCESS.BUS Interface Versatile Timer Unit Serial Debug Interface Power ManagementDMA Controller Development Support LQFP-128 Signal DescriptionsCP3BT26 LQFP-144 Bbclk ResetX1CKI X1CKO Name Pins Primary Function Alternate Alternate Function PG5 PG4Sdat PG6 X1CKI WR1 SelioWR0 CTS PE4 SLE CPU Architecture GENERAL-PURPOSE RegistersDedicated Address Registers 12 11 Reserved Processor Status Register PSRInterrupt Base Register Intbase No carry or borrow occurred Carry or borrow occurred Mode for the CR16B large model. Configuration Register CFGWhen the IDT has 16-bit entries, and all ex Is held in the Intbase register, which is not Addressing Modes Addb R1, R2Loadw 12R5, R6 Stacks Instruction SET Instruction Set Summary Mnemonic Operands Description Tbit AshudLshd LPR POP RetxPush Popret NOP StormpEiwait Wait Memory Operating EnvironmentIN/A BIU Control Registers BUS Interface Unit BIUBUS Cycles Empty 2 I/O Zone Configuration Register Iocfg Static Zone 0 Configuration Register SZCFG0 Static Zone 1 Configuration Register SZCFG1 Static Zone 2 Configuration Register SZCFG2WBR RBE Hold Wait Ipst Flash Program/Data Memory Access to PeripheralsWait and Hold States RAM Memory System Configuration Registers Module Configuration Register McfgSystem Configuration Registers Name Address Description Software Reset Register Swreset Module Status Register Mstat Flash Memory Flash Memory ProtectionFlash Memory Organization Flash Memory Operations Information Block Module Erase Main Block Page EraseMain Block Module Erase Main Block Write Boot Information Block WordsArea Flash Memory Interface Registers CPU Reset BehaviorBoot Area Start-Up Operation Empty Ispe Flash Memory Information Block Data Register Flash Memory 0 Write Enable Register FM0WER/FSM0WERFlash Memory 1 Write Enable Register FM1WER FMIBDR/FSMIBDR Flash Data Memory 0 Write Enable Register FSM0WER Flash Memory Control Register FmctrlFsmctrl Fsmstat FsmpsrFMSTART/FSMSTART Flash Memory End Time Reload Register FMEND/FSMEND FMRCV/FSMRCV FSMAR1 Flash Memory Auto-Read Register 0 FMAR0/ FSMAR0Flash Memory Auto-Read Register 2 FMAR2/ FSMAR2 Transfer Types DMA ControllerChannel Assignment DMA Channel Assignment Peripheral Trans Register Action Operation Modes Debug Mode Software DMA RequestDMA Controller Register SET Device B Address Counter Register ADCBn Device a Address Counter Register ADCAnDevice a Address Register ADRAn Device B Address Register ADRBn Block Length Register BLTRn DMA Control Register DMACNTLn DMA Status Register Dmastat VLD Chac OVRVLD Maskable Interrupts InterruptsNON-MASKABLE Interrupts Interrupt Controller Registers Interrupt Vector Register Ivct External NMI Trap Control and Status Register ExnmiNon-Maskable Interrupt Status Register Nmistat Interrupt Status Register 1 ISTAT1 Interrupt Enable and Mask Register 1 IENAM1Interrupt Enable and Mask Register 2 IENAM2 Interrupt Status Register 2 ISTAT2 Maskable Interrupts Assignment IRQ Number Description Maskable Interrupt SourcesNested Interrupts IRQ Number Description Triple Clock and Reset Triple Clock and Reset Module Type External Crystal NetworkCrystal Resonance Frequency Capacitor C1, C2 Capacitance PLL Clock Main ClockSlow Clock Min. Q factor Clock and Reset Registers POWER-ON ResetExternal Reset System Clock MODE20 Power Save Mode Power ManagementActive Mode Module Activity Summary Power Mode Clock Power Management Registers Name Address Description Idle Mode Power Management RegistersHalt Mode Power Management Control Register Pmmcr DHC HccmHcch Active Mode to Power Save Mode OHC OMC OLCOHC Software-Controlled Transition to Active Mode Entering Idle ModeEntering Halt Mode Wake-Up Transition to Active Mode Multi-Input Wake-Up Module Block Diagram Multi-Input Wake-Up Miwu Channel MULTI-INPUT WAKE-UP RegistersMiwu Sources Multi-Input Wake-Up Registers Name Address Description Wake-Up Enable Register WK0ENA Wake-Up Interrupt Enable Register WK0IENAWake-Up 1 Interrupt Enable Register WK1IENA Wake-Up 1 Edge Detection Register WK1EDG Wake-Up 1 Interrupt Control Register Wake-Up Interrupt Control RegisterWK0ICTL1 WK0ICTL2 WK1ICTL1 WK1ICTL2 Wake-Up 1 Pending Register WK1PND Wake-Up Pending Register WK0PNDWake-Up Pending Clear Register WK0PCL Wake-Up 1 Pending Clear Register WK1PCL Programming Procedures Input/Output Ports Port Registers Port Registers Address Description Port Data Output Register PxDOUT Port Alternate Function Register PxALTPort Data Input Register PxDIN Port Direction Register PxDIR Alternate Function Select Port High Drive Strength Register PxHDRVPort Alternate Function Select Register PxALTS Port Pin PxALTS = OPEN-DRAIN Operation X1CKI/BBCLK Bluetooth ControllerRF Interface Rfdata Sclk Serial InterfaceRfce Sdat Write Operation Serial Interface Write Timing Read Operation Bit, and register address for a read cycle. In the second First part of read cycle driven by CP3BT26. Address is 0Ah 15.3 LMX5251 POWER-UP Sequence 15.4 LMX5252 POWER-UP Sequence Bluetooth Sleep Mode Bluetooth Global RegistersBluetooth Sequencer RAM Bluetooth Shared Data RAM 16.0 12-Bit Analog to Digital Converter Functional DescriptionData Path ADC Voltage References OperationADC Clock Generation Pen-Down Detector Touchscreen Driver Configuration Touchscreen Interface RY2 Measuring Pen ForceRX2 RYP ADC Register SET ADC Operation in POWER-SAVING ModesFreeze ADC Registers Name Address Description Muxcfg Touchcfg ADC0/TSX+ ADC1/TSY+ ADC2/TSX ADC3/TSY Prefcfg NrefcfgClkdiv ADC Start Conversion Delay Register Adcscdly ADC Conversion Control Register AdccntrlADC Start Conversion Register Adcstart Adcoflw ADC Result Register AdcresltAdcresult Sign RNG Module Block Diagram Random Number Generator RNG Random Number Generator Register SET USB Controller Functional States Endpoint Operation TX Fifo RX Fifo Bidirectional Control Endpoint FIFO0 Operation Transmit Endpoint Fifo Operation TXFIFO1, TXFIFO2, TXFIFO3 USB Controller Registers Receive Endpoint Fifo Operation RXFIFO1, RXFIFO2, RXFIFO3USB Controller Registers Name Address Description Main Control Register Mcntrl USB Functional States Node Functional State Register NfsrNFS NFS Main Event Register Maev Main Mask Register MamskAlternate Event Register Altev Alternate Mask Register Altmsk Transmit Event Register TxevTransmit Mask Register Txmsk Receive Event Register Rxev NAK Event Register Nakev Receive Mask Register RxmskNAK Mask Register Nakmsk Fifo Warning Event Register Fwev Frame Number High Byte Register FNHFifo Warning Mask Register Fwmsk Dsrc DMA Event Register Dmaev Mirror Register MIR DMA Error Register DmaerrDMA Mask Register Dmamsk DMA Count Register Dmacnt Transmit Command 0 Register TXC0 Endpoint Control 0 Register EPC0Transmit Status 0 Register TXS0 Receive Command 0 Register RXC0 Transmit Data 0 Register TXD0Receive Status 0 Register RXS0 Receive Data 0 Register RXD0 Endpoint Control Register n EPCnTransmit Status Register n TXSn Last Transmit Command Register n TXCnTfwl RFF Tfwl Transmit Fifo Warning LimitReceive Status Register n RXSn Bytes Remaining in Fifo Receive Fifo Warning Limit Receive Command Register n RXCn Receive Data Register n RXDTransceiver Interface Rfwl Can Module Can Block Diagram Basic can Concepts Start of Frame SOF Can Frame TypesCan Frame Fields Arbitration Field Cyclic Redundancy Check CRC Data Length Code DLCData Field ACK Field Remote Frame Data FieldCyclic Redundancy Check Field CRC Error Frame Error Frame Overload Frame Bit CRC Error Stuff ErrorForm Error Acknowledgment Error Error Passive Error ActiveError Warning Error Counters Synchronization Bit Time LogicCan Bit Time Bit Timing Message Transfer CKI Two 32-bit masks are used to filter unwanted messages Acceptance FilteringExample 1 Acceptance of a Single Identifier From the can bus Gmask and BMASK. shows Receive Structure 120 Writing to Buffer Status Code During Receive ProcedureReceive Timing Rxbusy Buffer Read Routine Bufflock Enabled 122 Transmit Structure Transmit SchedulingTransmit Priority Txpri PRI Interrupts TX Buffer States Time Stamp Counter IRQ IST3 IST2 IST1 IST0 Message Buffer Organization CPU Access to can Registers/MemoryMemory Organization Message Buffer Map Address Register Can Controller Registers Can Controller Registers Name Address DescriptionBuffer Status/Control Register Cnstat Buffer Status Section of the Cnstat Register ST3 DIR ST2 ST1 ST0 BusyBuffer Status Storage of Standard Messages Data Length CodingDLC Standard Frame with 8 Data Bytes Address Buffer Register Extended Messages with 8 Data Bytes Address Buffer Register Cnstat DLCPRI SRR Storage of Remote Messages Frame is received, the contents of these registers will beContents of these registers are ignored. If a remote Extended Remote Frame Address Buffer Register Can Global Configuration Register Cgcr When the Loopback bit is set, all messages Listen Only bit can be used to configureWhen the Ignore Acknowledge bit is set, Dress, as shown in Figure SJW RTR IDE TSEG1TSEG2 Xrtr Basic Mask BM2818 Can Interrupt Enable Register CienBasic Mask Register BMSKB/BMSKX BM170 IRQ Error Field Identifier Can Error Counter Register CanecCan Error Diagnostic Register Cediag EFID30 System START-UP and MULTI-INPUT WAKE-UP Can Timer Register CtmrExternal can Pins Signal Name Type Description External Connection Acceptance Filter Considerations Minimum Clock Frequency Requirements Baud RateBit Time Logic Calculation Examples Remote Frames Usage Hint Audio Interface Signals Advanced Audio InterfaceAudio Interface Modes Synchronous Mode Normal ModeDMA Support 145 BIT Clock Generation Clock ConfigurationFrame Clock Generation Audio Interface Operation Fifo Operation TransmitDMA Operation Receive Frame Sync Signal Communication OptionsData Word Length Audio Control Data Short and Long Frame Sync Pulses IOM-2 Mode Loopback Mode150 Freeze Mode Audio Interface RegistersAudio Interface Registers Name Address Description Audio Receive DMA Register n ARDRn Audio Receive Fifo Register ArfrAudio Transmit Fifo Register Atfr Audio Transmit DMA Register n ATDRn SCS Audio Global Configuration Register AgcrSlots per Mode Frame FSL Txeic Txic Rxeic Rxic Rxie Audio Interrupt Status and Control Register AiscrTxeip Txip Rxeip Rxip Txeie Txie Rxeie Rxie Txeip Rxsa Bit Slots Enabled Rxdsa Bit Slots Enabled For DMAAudio Receive Status and Control Register Arscr Txsa Bit Slots Enabled Txdsa Bit Slots Enabled For DMAAudio Transmit Status and Control Register Atscr RMD Audio Clock Control Register AccrAudio DMA Control Register Admacr DMA Request Condition CVSD/PCM Conversion Module OperationPCM Conversions Cvsd to PCM Conversion Cvsd ConversionPCM to Cvsd Conversion Interrupt Generation CVSD/PCM Converter Registers Linearout Cvsd Status Register Cvstat Uart Modules Functional OverviewUart Operation Uart Block Diagram Uart Asynchronous Communication Diagnostic Mode Frame Format Selection Prescaler Factors Prescaler Factor Break Generation and Detection Parity Generation and Detection Uart Registers Uart Registers Name Address Description Uart Transmit Data Buffer UnTBUF Uart Baud Rate Divisor UnBAUDUart Receive Data Buffer UnRBUF Uart Frame Select Register UnFRS Uart Mode Select Register 1 UnMDSL1 Uart Status Register UnSTAT UOVSR30 Uart Interrupt Control Register UnICTRLUart Oversample Rate Register UnOVR Oversampling Rate Uart Sample Position Register UnSPOS Uart Mode Select Register 2 UnMDSL2Baud Rate Calculations Oversampling Rate Sample Position 173 174 Microwire Interface Microwire/SPI InterfaceMicrowire Operation Shifting Writing Clocking Modes Master Mode Normal Mode Scidl = Slave Mode Microwire Interrupt Trigger Condition Status Enable BitMWCTRL1 Microwire Interface Registers Mwen Scdv Microwire Status Register MwstatSCM OVR RBF BSY Data Transactions ACCESS.bus InterfaceACB Protocol Overview Start and Stop Acknowledge Cycle Addressing Transfer FormatsArbitration on the Bus ACB Functional Description Slave Mode Master Error DetectionsBus Idle Error Recovery Slave Error Detections ACCESS.BUS Interface Registers ACB Control Status Register Acbcst Start TgsclACB Control Register 1 ACBCTL1 Stop ACB Control Register 2 ACBCTL2 ACB Control Register 3 ACBCTL3 Saen Addr Usage HintsACB Own Address Register 1 ACBADDR1 Saen Avoiding Bus Error During Write Transaction 190 191 Timer T0 Operation Timing and Watchdog ModuleTWM Structure TWM Registers Power Save Mode OperationWatchdog Operation Register Locking Mdiv T0IN TWMT0 Control and Status Register T0CSR Watchdog Programming ProcedureWatchdog Service Data Match Register Wdsdm Watchdog Count Register Wdcnt Clock Source Block Multi-Function TimerTimer Structure 196 Limitations in Low-Power Modes Timer Operating ModesPulse Accumulate Mode Counter Clock Source Select Mode 1 Processor-Independent PWM 198 Mode 2 Dual Input Capture Dual-Input Capture Mode Mode 3 Dual Independent Timer/Counter 200 Mode 4 Input Capture Plus Timer Input Capture Plus Timer Mode Taen Timer InterruptsTimer I/O Functions Tben Timer Registers Timer Mode Control Register Tctrl Reload/Capture a Register TcraReload/Capture B Register Tcrb Timer Interrupt Control Register Tictl Timer Interrupt Clear Register Ticlr Versatile Timer Unit VTU VTU Functional Description206 Dual 8-bit PWM Mode VTU PWM Generation VTU 16-bit PWM Mode Dual 16-Bit Capture Mode 208 VTU Dual 16-bit Capture Mode Low Power Mode ISE Mode operation Mode Control Register Mode VTU RegistersVTU Registers Name Address Description CxEDG Capture Counter Reset Interrupt Control Register Intctl Clock Prescaler Register 1 CLK1PS Interrupt Pending Register IntpndClock Prescaler Register 2 CLK2PS Duty Cycle/Capture Register n DTYCAPx Counter Register n COUNTxCNTx Period/Capture Register n PERCAPx Bluetooth LLC Registers Register Map Register Name Size Address Access Value After Comments Type USB Node Registers EPC2 EPC1TXC1 EPC4 Can Module Message Buffers Can Registers DMA Controller Bus Interface Unit System Configuration Flash Program Memory InterfaceFlash Data Memory Interface Triple Clock + Reset CVSD/PCM Converter Multi-Input Wake-Up General-Purpose I/O Ports Register Name Size Address Comments Type Advanced Audio Interface Interrupt Control Unit UART0 UART1 UART2 UART3 ACCESS.bus Multi-Function TimerTiming and Watchdog Versatile Timer Unit ADC Rngd RNGRngcst Word FF F284h Register Bit Fields USB Nakev OUT Nakmsk Fwev RXWARN31 Setup Toggle Rxlast Rcount RXC0IGN Ignout Rxen Setup EPC1 Fwmsk RXWARN31 Can Control Status Memory Registers Dmac TBI Register System Configuration RegistersBIU Flash Flash Data Memory CVSD/PCM CLK3RES Gpio Registers PMM RegisterMIWU16 AAI ICU Registers Uart MWSPI16 ACB RegistersMFT16 VTU Rngd RngcstImsk Rngdivh Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Conditions Min Max Units TBD IOOff LSB Symbol Parameter Conditions Min Typ Max UnitsINL DNL Flash Memory ON-CHIP Programming Reset and NMI Input Signals Output Signal LevelsClock and Reset Timing TRI-STATE NMI Signal Timing Clock Timing Uart Output Signals Uart Timing Port Output Signals 30.9 I/O Port Timing AAI Output Signals Advanced Audio Interface AAI Timing Transmit Timing, Short Frame Sync Receive Timing, Long Frame Sync Microwire/SPI Input Signals MICROWIRE/SPI TimingMicrowire/SPI Signals Symbol Description Reference Min ns Microwire/SPI Output Signals Alternate Mode After RE On MSK Propagation Time Normal Mode After FE onMicrowire Data Out Valid 254 255 Microwire Transaction Timing, Alternate Mode, Scidl = 256 257 ACCESS.BUS Timing ACCESS.bus Output Signals 259 ACB Data Timing 260 USB Port AC Characteristics MULTI-FUNCTION Timer MFT Timing TIOx Input Low Time RE on CLK Versatile Timing Unit VTU TimingTIOx Input High Time Rising Edge RE on CLK 262 External Bus Output Signals External BUS Timing Early Write Between Normal Read Cycles No Wait States 264 265 Consecutive Normal Read Cycles Burst, No Wait States 266 267 Early Write Between Fast Read Cycles 268 PWR Pin AssignmentsLQFP-128 Package X1CKO X1CKI X2CKI X2CKO ENV2 Reset TMSAvcc PWR Adgnd Advcc Uvcc SDA ADC0 TSX+ PF0 MSK/TIO1 PE0 RXD0 Gpio PE1 TXD0 PE2 RTS PE3 CTS PE4 CKX/TB PE5SRFS/NMI PF1 MDIDO/TIO2 LQFP-144 Package 272 ADC5 MUXOUT1 SCL SDA ADC0 TSX+ADC4 MUXOUT0 ADC7 Adcin Pin Name Alternate Functions Pin Number Type A11 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13A12 A10 Revision History Revision HistoryDate Major Changes From Previous Version Physical Dimensions millimeters unless otherwise noted LQFP-128 Package LQFP-144 Package Form when properly used in accordance with instructions Life Support PolicyBanned Substance Compliance