National CP3BT26 manual Dhc, Hccm, Hcch

CP3BT26

HALT	The Halt Mode bit indicates whether the de-	DHC	The Disable High-Frequency (PLL) Clock bit
	vice is in Halt mode. Before entering Halt		and the CRCTRL.PLLPWD bit may be used to
	mode, the WBPSM bit must be set. When the		disable the PLL in Power Save and Idle
	HALT bit is written with 1, the device enters		modes. When the DHC bit is clear (and PLL-
	the Halt mode at the execution of the next		PWD = 0), the PLL is enabled in these modes.
	WAIT instruction. When in HALT mode, the		If the DHC bit is set, the PLL is disabled in
	PMM stops the System Clock and then turns		Power Save and Idle mode. In Active mode
	off the PLL and the high-frequency oscillator.		with the CRCTRL.PLLPWD bit set, the PLL is
	The HALT bit can be set and cleared by soft-		enabled without regard to the DHC value. In
	ware. The Halt mode is exited by a hardware		Halt mode, the PLL is disabled without regard
	wake-up event. When this signal is set high,		to the DMC value. The DHC bit is cleared by
	the oscillator is started. After the oscillator has		hardware when a hardware wake-up event is
	stabilized, the HALT bit is cleared by the hard-		detected.
	ware.		0 – PLL is disabled only by entering Halt
	0 – Device is not in Halt mode.		mode or setting the CRCTRL.PLLPWD
	1 – Device is in Halt mode.		bit.
WBPSM	When the Wait Before Power Save Mode bit is		1 – PLL is also disabled in Power Save or Idle
	clear, a switch from Active mode to Power		mode.
	Save mode only requires setting the PSM bit.	HCCM	The Hardware Clock Control for Main Clock
	When the WBPSM bit is set, a switch from Ac-		bit may be used in Power Save and Idle
	tive mode to Power Save, Idle, or Halt mode is		modes to disable the high-frequency oscillator
	performed by setting the PSM, IDLE or HALT		conditionally, depending on whether the Blue-
	bit, respectively, and then executing a WAIT		tooth LLC is in Sleep mode. The DMC bit must
	instruction. Also, if the DMC or DHC bits are		be clear for this mechanism to operate. The
	set, the high-frequency oscillator and PLL		HCCM bit is automatically cleared when the
	may be disabled only after a WAIT instruction		device enters Active mode.
	is executed and the Power Save, Idle, or Halt		0 – High-frequency oscillator is disabled in
	mode is entered.		Power Save or Idle mode only if the DMC
	0 – Mode transitions may occur immediately.		bit is set.
	1 – Mode transitions are delayed until the		1 – High-frequency oscillator is also disabled
	next WAIT instruction is executed.		if the Bluetooth LLC is idle.
DMC	The Disable Main Clock bit may be used to	HCCH	The Hardware Clock Control for High-Fre-
	disable the high-frequency oscillator in Power		quency (PLL) bit may be used in Power Save
	Save and Idle modes. In Active mode, the		and Idle modes to disable the PLL condition-
	high-frequency oscillator is enabled without		ally, depending on whether the Bluetooth LLC
	regard to the DMC value. In Halt mode, the		is in Sleep mode. The DHC bit and the CRC-
	high-frequency oscillator is disabled without		TRL.PLLPWD bit must be clear for this mech-
	regard to the DMC value. The DMC bit is		anism to operate. The HCCH bit is
	cleared by hardware when a hardware wake-		automatically cleared when the device enters
	up event is detected.		Active mode.
	0 – High-frequency oscillator is only disabled		0 – PLL is disabled in Power Save or Idle
	in Halt mode or when disabled by the		mode only if the DMC bit or the CRC-
	HCC mechanism.		TRL.PLLPWD bit is set.
	1 – High-frequency oscillator is also disabled		1 – PLL is also disabled if the Bluetooth LLC
	in Power Save and Idle modes.		is idle.

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