National CP3BT26 manual Flash Memory ON-CHIP Programming

CP3BT26

30.5FLASH MEMORY ON-CHIP PROGRAMMING

Symbol	Parameter	Conditions	Min	Max	Units
t	Program/Erase to NVSTR Setup Timea		5	-	µs
START	(NVSTR = Non-Volatile Storage
tTRAN	NVSTR to Program Setup Timeb		10	-	µs
t	Programming Pulse Widthc		20	40	µs
PROG
tPERASE	Page Erase Pulse Widthd		20	-	ms
t	Module Erase Pulse Widthe		200	-	ms
MERASE
t	NVSTR Hold Timef		5	-	µs
END
t	NVSTR Hold Time (Module Erase)g		100	-	µs
MEND
tRCV	Recovery Timeh		1	-	µs
tHV	Cumulative Program High Voltage Period For	128K program blocks	-	8	ms
	Each Row After Erasei
tHV		8K data block	-	4	ms
	Write/Erase Endurance		20,000	-	cycles
	Data Retention	25°C	100	-	years

a.Program/erase to NVSTR Setup Time is determined by the following equation:

tSTART = Tclk × (FTDIV + 1) × (FTSTART + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTSTART is the contents of the FMSTART or FSMSTART register

b.NVSTR to Program Setup Time is determined by the following equation:

tTRAN = Tclk × (FTDIV + 1) × (FTTRAN + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTTRAN is the contents of the FMTRAN or FSMTRAN register

c.Programming Pulse Width is determined by the following equation:

tPROG = Tclk × (FTDIV + 1) × 8 × (FTPROG + 1), where Tclk is the System Clock period, FTDIV is the con- tents of the FMPSR or FSMPSR register, and FTPROG is the contents of the FMPROG or FSMPROG regis- ter

d.Page Erase Pulse Width is determined by the following equation:

tPERASE = Tclk × (FTDIV + 1) × 4096 × (FTPER + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPER is the contents of the FMPERASE or FSMPER- ASE register

e.Module Erase Pulse Width is determined by the following equation:

tMERASE = Tclk × (FTDIV + 1) × 4096 × (FTMER + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMER is the contents of the FMMERASE0 or FSMMERASE0 register

f.NVSTR Hold Time is determined by the following equation:

tEND = Tclk × (FTDIV + 1) × (FTEND + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTEND is the contents of the FMEND or FSMEND register

g.NVSTR Hold Time (Module Erase) is determined by the following equation:

tMEND = Tclk × (FTDIV + 1) × 8 × (FTMEND + 1), where Tclk is the System Clock period, FTDIV is the con- tents of the FMPSR or FSMPSR register, and FTMEND is the contents of the FMMEND or FSMMEND regis- ter

h.Recovery Time is determined by the following equation:

tRCV = Tclk × (FTDIV + 1) × (FTRCV + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register

i.Cumulative program high voltage period for each row after erase tHV is the accumulated duration a flash cell is exposed to the programming voltage after the last erase cycle.

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