National CP3BT26 manual ACB Functional Description

24.2ACB FUNCTIONAL DESCRIPTION

The ACB module provides the physical layer for an AC- CESS.bus compliant serial interface. The module is config- urable as either a master or slave device. As a slave, the ACB module may issue a request to become the bus mas- ter.

24.2.1Master Mode

An ACCESS.bus transaction starts with a master device re- questing bus mastership. It sends a Start Condition, fol- lowed by the address of the device it wants to access. If this transaction is successfully completed, software can assume that the device has become the bus master.

For a device to become the bus master, software should perform the following steps:

1.Set the ACBCTL1.START bit, and configure the ACBCTL1.INTEN bit to the desired operation mode (Polling or Interrupt). This causes the ACB to issue a Start Condition on the ACCESS.bus, as soon as the ACCESS.bus is free (ACBCST.BB=0). It then stalls the bus by holding SCL low.

2.If a bus conflict is detected, (i.e., some other device pulls down the SCL signal before this device does), the ACBST.BER bit is set.

3.If there is no bus conflict, the ACBST.MASTER and ACBST.SDAST bits are set.

4.If the ACBCTL1.INTEN bit is set, and either the ACB- ST.BER bit or the ACBST.SDAST bit is set, an interrupt is sent to the ICU.

Sending the Address Byte

Once this device is the active master of the ACCESS.bus (ACBST.MASTER = 1), it can send the address on the bus. The address should not be this device’s own address as specified in the ACBADDR.ADDR field if the ACBAD- DR.SAEN bit is set or the ACBADDR2.ADDR field if the ACBADDR2.SAEN bit is set, nor should it be the global call address if the ACBST.GCMTCH bit is set.

To send the address byte use the following sequence:

1.Configure the ACBCTL1.INTEN bit according to the de- sired operation mode. For a receive transaction where software wants only one byte of data, it should set the ACBCTL1.ACK bit. If only an address needs to be sent, set the ACBCTL1.STASTRE bit.

2.Write the address byte (7-bit target device address), and the direction bit, to the ACBSDA register. This causes the module to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to the ACBST.NEGACK bit. During the transac- tion, the SDA and SCL signals are continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted, the ACBST.BER bit is set, and the ACBST.MASTER bit is cleared.

3.If the ACBCTL1.STASTRE bit is set, and the transac- tion was successfully completed (i.e., both the ACB- ST.BER and ACBST.NEGACK bits are cleared), the ACBST.STASTR bit is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the ACBCTL1.INTE bit is set, it also sends an interrupt to the core.

4.If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither the ACBST.NEGACK nor ACBST.BER bit is set, and no other master has accessed the device), the ACB- ST.SDAST bit is set to indicate that the module is wait- ing for service.

5.If the requested direction is receive, the start transac- tion was completed successfully, and the ACBCTL1.STASTRE bit is clear, the module starts re- ceiving the first byte automatically.

6.Check that both the ACBST.BER and ACBST.NEGACK bits are clear. If the ACBCTL1.INTEN bit is set, an in- terrupt is generated when either the ACBST.BER or ACBST.NEGACK bit is set.

Master Transmit

After becoming the bus master, the device can start trans- mitting data on the ACCESS.bus. To transmit a byte, soft- ware must:

1.Check that the BER and NEGACK bits in the ACBST register are clear and the ACBST.SDAST bit is set. Al- so, if the ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear.

2.Write the data byte to be transmitted to the ACBSDA register.

When the slave responds with a negative acknowledge, the ACBST.NEGACK bit is set and the ACBST.SDAST bit re- mains cleared. In this case, if the ACBCTL1.INTEN bit is set, an interrupt is sent to the core.

Master Receive

After becoming the bus master, the device can start receiv- ing data on the ACCESS.bus. To receive a byte, software must:

1.Check that the ACBST.SDAST bit is set and the ACB- ST.BER bit is clear. Also, if the ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear.

2.Set the ACBCTL1.ACK bit, if the next byte is the last byte that should be read. This causes a negative ac- knowledge to be sent.

3.Read the data byte from the ACBSDA register.

Master Stop

A Stop Condition may be issued only when this device is the active bus master (ACBST.MASTRER = 1). To end a trans- action, set the ACBCTL1.STOP bit before clearing the cur- rent stall bit (i.e., the ACBST.SDAST, ACBST.NEGACK, or ACBST.STASTR bit). This causes the module to send a Stop Condition immediately, and clear the ACBCTL1.STOP bit.

CP3BT26

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