Early Write Between Fast Read Cycles, 268

CP3BT26			Fast Read		Early Write		Fast Read
CP3BT26	Bus State	Tidle	T1-2	T1	T2	T3	T1-2	T1
	CLK
			t4	t4, t12
	A[21:0]
	A22 ('13 only)
	SELx
	(y ≠ x)	t5, t12
		t5, t12		t5, t12
				t5, t12
	SELy			t1
	(y ≠ x)			t1
				t2
	D[15:0]			In	Out			In
	RD
		t5, t12		t5, t12
				t5, t12
	WR[1:0]
								DS128
			Figure 135. Early Write Between Fast Read Cycles
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National CP3BT26 manual Early Write Between Fast Read Cycles, 268

Contents

Block Diagram General DescriptionMAY National Semiconductor Corporation Table of Contents Features Device Overview Bluetooth LLC Can InterfaceQuad Uart Advanced Audio Interface MICROWIRE/SPI ACCESS.BUS InterfaceMULTI-FUNCTION Timer Versatile Timer Unit Power Management DMA ControllerSerial Debug Interface Development Support Signal Descriptions CP3BT26LQFP-128 LQFP-144 Reset X1CKIBbclk X1CKO Name Pins Primary Function Alternate Alternate Function PG4 SdatPG5 PG6 X1CKI Selio WR0WR1 CTS PE4 SLE GENERAL-PURPOSE Registers CPU ArchitectureDedicated Address Registers Processor Status Register PSR Interrupt Base Register Intbase12 11 Reserved No carry or borrow occurred Carry or borrow occurred Configuration Register CFG When the IDT has 16-bit entries, and all exMode for the CR16B large model. Is held in the Intbase register, which is not Addb R1, R2 Addressing ModesLoadw 12R5, R6 Stacks Instruction SET Instruction Set Summary Mnemonic Operands Description Ashud LshdTbit LPR Retx PushPOP Popret Stormp EiwaitNOP Wait Operating Environment MemoryIN/A BUS Interface Unit BIU BUS CyclesBIU Control Registers Empty 2 I/O Zone Configuration Register Iocfg Static Zone 0 Configuration Register SZCFG0 Static Zone 2 Configuration Register SZCFG2 Static Zone 1 Configuration Register SZCFG1WBR RBE Hold Wait Ipst Access to Peripherals Wait and Hold StatesFlash Program/Data Memory RAM Memory Module Configuration Register Mcfg System Configuration RegistersSystem Configuration Registers Name Address Description Software Reset Register Swreset Module Status Register Mstat Flash Memory Protection Flash MemoryFlash Memory Organization Flash Memory Operations Main Block Page Erase Main Block Module EraseInformation Block Module Erase Main Block Write Information Block Words BootArea CPU Reset Behavior Boot Area Start-Up OperationFlash Memory Interface Registers Empty Ispe Flash Memory 0 Write Enable Register FM0WER/FSM0WER Flash Memory 1 Write Enable Register FM1WERFlash Memory Information Block Data Register FMIBDR/FSMIBDR Flash Memory Control Register Fmctrl Flash Data Memory 0 Write Enable Register FSM0WERFsmctrl Fsmpsr FsmstatFMSTART/FSMSTART Flash Memory End Time Reload Register FMEND/FSMEND Flash Memory Auto-Read Register 0 FMAR0/ FSMAR0 FMRCV/FSMRCV FSMAR1Flash Memory Auto-Read Register 2 FMAR2/ FSMAR2 DMA Controller Channel AssignmentTransfer Types DMA Channel Assignment Peripheral Trans Register Action Operation Modes Software DMA Request Debug ModeDMA Controller Register SET Device a Address Counter Register ADCAn Device a Address Register ADRAnDevice B Address Counter Register ADCBn Device B Address Register ADRBn Block Length Register BLTRn DMA Control Register DMACNTLn VLD Chac OVR DMA Status Register DmastatVLD Interrupts NON-MASKABLE InterruptsMaskable Interrupts Interrupt Controller Registers External NMI Trap Control and Status Register Exnmi Interrupt Vector Register IvctNon-Maskable Interrupt Status Register Nmistat Interrupt Enable and Mask Register 1 IENAM1 Interrupt Enable and Mask Register 2 IENAM2Interrupt Status Register 1 ISTAT1 Interrupt Status Register 2 ISTAT2 Maskable Interrupt Sources Nested InterruptsMaskable Interrupts Assignment IRQ Number Description IRQ Number Description Triple Clock and Reset Triple Clock and Reset Module External Crystal Network Crystal Resonance FrequencyType Capacitor C1, C2 Capacitance Main Clock Slow ClockPLL Clock Min. Q factor POWER-ON Reset External ResetClock and Reset Registers System Clock MODE20 Power Management Active ModePower Save Mode Module Activity Summary Power Mode Clock Idle Mode Power Management Registers Halt ModePower Management Registers Name Address Description Power Management Control Register Pmmcr Hccm DHCHcch OHC OMC OLC Active Mode to Power Save ModeOHC Entering Idle Mode Entering Halt ModeSoftware-Controlled Transition to Active Mode Wake-Up Transition to Active Mode Multi-Input Wake-Up Module Block Diagram Multi-Input Wake-Up MULTI-INPUT WAKE-UP Registers Miwu SourcesMiwu Channel Multi-Input Wake-Up Registers Name Address Description Wake-Up Interrupt Enable Register WK0IENA Wake-Up 1 Interrupt Enable Register WK1IENAWake-Up Enable Register WK0ENA Wake-Up 1 Edge Detection Register WK1EDG Wake-Up Interrupt Control Register WK0ICTL1 WK0ICTL2Wake-Up 1 Interrupt Control Register WK1ICTL1 WK1ICTL2 Wake-Up Pending Register WK0PND Wake-Up Pending Clear Register WK0PCLWake-Up 1 Pending Register WK1PND Wake-Up 1 Pending Clear Register WK1PCL Programming Procedures Input/Output Ports Port Registers Port Registers Address Description Port Alternate Function Register PxALT Port Data Input Register PxDINPort Data Output Register PxDOUT Port Direction Register PxDIR Port High Drive Strength Register PxHDRV Port Alternate Function Select Register PxALTSAlternate Function Select Port Pin PxALTS = OPEN-DRAIN Operation Bluetooth Controller RF InterfaceX1CKI/BBCLK Rfdata Serial Interface RfceSclk Sdat Write Operation Serial Interface Write Timing Read Operation Bit, and register address for a read cycle. In the second First part of read cycle driven by CP3BT26. Address is 0Ah 15.3 LMX5251 POWER-UP Sequence 15.4 LMX5252 POWER-UP Sequence Bluetooth Global Registers Bluetooth Sleep ModeBluetooth Sequencer RAM Bluetooth Shared Data RAM Functional Description 16.0 12-Bit Analog to Digital ConverterData Path Operation ADC Clock GenerationADC Voltage References Pen-Down Detector Touchscreen Driver Configuration Touchscreen Interface Measuring Pen Force RX2RY2 RYP ADC Operation in POWER-SAVING Modes FreezeADC Register SET ADC Registers Name Address Description Muxcfg Touchcfg ADC0/TSX+ ADC1/TSY+ ADC2/TSX ADC3/TSY Nrefcfg PrefcfgClkdiv ADC Conversion Control Register Adccntrl ADC Start Conversion Delay Register AdcscdlyADC Start Conversion Register Adcstart ADC Result Register Adcreslt AdcresultAdcoflw Sign RNG Module Block Diagram Random Number Generator RNG Random Number Generator Register SET USB Controller Functional States Endpoint Operation TX Fifo RX Fifo Bidirectional Control Endpoint FIFO0 Operation Transmit Endpoint Fifo Operation TXFIFO1, TXFIFO2, TXFIFO3 Receive Endpoint Fifo Operation RXFIFO1, RXFIFO2, RXFIFO3 USB Controller RegistersUSB Controller Registers Name Address Description Main Control Register Mcntrl Node Functional State Register Nfsr NFSUSB Functional States NFS Main Mask Register Mamsk Main Event Register MaevAlternate Event Register Altev Transmit Event Register Txev Alternate Mask Register AltmskTransmit Mask Register Txmsk Receive Mask Register Rxmsk Receive Event Register Rxev NAK Event Register NakevNAK Mask Register Nakmsk Frame Number High Byte Register FNH Fifo Warning Event Register FwevFifo Warning Mask Register Fwmsk Dsrc DMA Event Register Dmaev DMA Error Register Dmaerr DMA Mask Register DmamskMirror Register MIR DMA Count Register Dmacnt Endpoint Control 0 Register EPC0 Transmit Command 0 Register TXC0Transmit Status 0 Register TXS0 Transmit Data 0 Register TXD0 Receive Command 0 Register RXC0Receive Status 0 Register RXS0 Endpoint Control Register n EPCn Receive Data 0 Register RXD0Transmit Status Register n TXSn Transmit Command Register n TXCn TfwlLast RFF Transmit Fifo Warning Limit Receive Status Register n RXSnTfwl Bytes Remaining in Fifo Receive Command Register n RXCn Receive Data Register n RXD Transceiver InterfaceReceive Fifo Warning Limit Rfwl Can Module Can Block Diagram Basic can Concepts Can Frame Types Can Frame FieldsStart of Frame SOF Arbitration Field Data Length Code DLC Data FieldCyclic Redundancy Check CRC ACK Field Data Field Remote FrameCyclic Redundancy Check Field CRC Error Frame Error Frame Overload Frame Stuff Error Form ErrorBit CRC Error Acknowledgment Error Error Active Error WarningError Passive Error Counters Bit Time Logic Can Bit TimeSynchronization Bit Timing Message Transfer CKI Acceptance Filtering Example 1 Acceptance of a Single IdentifierTwo 32-bit masks are used to filter unwanted messages From the can bus Gmask and BMASK. shows Receive Structure 120 Receive Procedure Receive TimingWriting to Buffer Status Code During Rxbusy Buffer Read Routine Bufflock Enabled 122 Transmit Scheduling Transmit StructureTransmit Priority Txpri PRI Interrupts TX Buffer States Time Stamp Counter IRQ IST3 IST2 IST1 IST0 CPU Access to can Registers/Memory Memory OrganizationMessage Buffer Organization Message Buffer Map Address Register Can Controller Registers Name Address Description Can Controller RegistersBuffer Status/Control Register Cnstat ST3 DIR ST2 ST1 ST0 Busy Buffer Status Section of the Cnstat RegisterBuffer Status Data Length Coding DLCStorage of Standard Messages Standard Frame with 8 Data Bytes Address Buffer Register Cnstat DLC Extended Messages with 8 Data Bytes Address Buffer RegisterPRI SRR Frame is received, the contents of these registers will be Contents of these registers are ignored. If a remoteStorage of Remote Messages Extended Remote Frame Address Buffer Register Can Global Configuration Register Cgcr Listen Only bit can be used to configure When the Ignore Acknowledge bit is set,When the Loopback bit is set, all messages Dress, as shown in Figure SJW TSEG1 TSEG2RTR IDE Xrtr Can Interrupt Enable Register Cien Basic Mask Register BMSKB/BMSKXBasic Mask BM2818 BM170 IRQ Can Error Counter Register Canec Can Error Diagnostic Register CediagError Field Identifier EFID30 Can Timer Register Ctmr External can Pins Signal Name Type DescriptionSystem START-UP and MULTI-INPUT WAKE-UP External Connection Minimum Clock Frequency Requirements Baud Rate Bit Time Logic Calculation ExamplesAcceptance Filter Considerations Remote Frames Usage Hint Advanced Audio Interface Audio Interface SignalsAudio Interface Modes Normal Mode Synchronous ModeDMA Support 145 Clock Configuration Frame Clock GenerationBIT Clock Generation Audio Interface Operation Transmit DMA OperationFifo Operation Receive Communication Options Frame Sync SignalData Word Length Audio Control Data Short and Long Frame Sync Pulses Loopback Mode IOM-2 Mode150 Audio Interface Registers Freeze ModeAudio Interface Registers Name Address Description Audio Receive Fifo Register Arfr Audio Transmit Fifo Register AtfrAudio Receive DMA Register n ARDRn Audio Transmit DMA Register n ATDRn Audio Global Configuration Register Agcr Slots per Mode FrameSCS FSL Audio Interrupt Status and Control Register Aiscr Txeip Txip Rxeip Rxip Txeie Txie Rxeie RxieTxeic Txic Rxeic Rxic Rxie Txeip Rxdsa Bit Slots Enabled For DMA Rxsa Bit Slots EnabledAudio Receive Status and Control Register Arscr Txdsa Bit Slots Enabled For DMA Txsa Bit Slots EnabledAudio Transmit Status and Control Register Atscr Audio Clock Control Register Accr Audio DMA Control Register AdmacrRMD DMA Request Condition Operation CVSD/PCM Conversion ModulePCM Conversions Cvsd Conversion PCM to Cvsd ConversionCvsd to PCM Conversion Interrupt Generation CVSD/PCM Converter Registers Linearout Cvsd Status Register Cvstat Functional Overview Uart ModulesUart Operation Uart Block Diagram Uart Asynchronous Communication Diagnostic Mode Frame Format Selection Prescaler Factors Prescaler Factor Break Generation and Detection Parity Generation and Detection Uart Registers Uart Registers Name Address Description Uart Baud Rate Divisor UnBAUD Uart Receive Data Buffer UnRBUFUart Transmit Data Buffer UnTBUF Uart Frame Select Register UnFRS Uart Mode Select Register 1 UnMDSL1 Uart Status Register UnSTAT Uart Interrupt Control Register UnICTRL Uart Oversample Rate Register UnOVRUOVSR30 Oversampling Rate Uart Mode Select Register 2 UnMDSL2 Baud Rate CalculationsUart Sample Position Register UnSPOS Oversampling Rate Sample Position 173 174 Microwire/SPI Interface Microwire OperationMicrowire Interface Shifting Writing Clocking Modes Master Mode Normal Mode Scidl = Microwire Interrupt Trigger Condition Status Enable Bit Slave ModeMWCTRL1 Microwire Interface Registers Mwen Microwire Status Register Mwstat SCMScdv OVR RBF BSY ACCESS.bus Interface ACB Protocol OverviewData Transactions Start and Stop Addressing Transfer Formats Acknowledge CycleArbitration on the Bus ACB Functional Description Master Error Detections Bus Idle Error RecoverySlave Mode Slave Error Detections ACCESS.BUS Interface Registers ACB Control Status Register Acbcst Tgscl ACB Control Register 1 ACBCTL1Start Stop ACB Control Register 2 ACBCTL2 ACB Control Register 3 ACBCTL3 Usage Hints ACB Own Address Register 1 ACBADDR1Saen Addr Saen Avoiding Bus Error During Write Transaction 190 191 Timing and Watchdog Module Timer T0 OperationTWM Structure Power Save Mode Operation Watchdog OperationTWM Registers Register Locking Mdiv T0IN Watchdog Programming Procedure Watchdog Service Data Match Register WdsdmTWMT0 Control and Status Register T0CSR Watchdog Count Register Wdcnt Multi-Function Timer Timer StructureClock Source Block 196 Timer Operating Modes Pulse Accumulate ModeLimitations in Low-Power Modes Counter Clock Source Select Mode 1 Processor-Independent PWM 198 Mode 2 Dual Input Capture Dual-Input Capture Mode Mode 3 Dual Independent Timer/Counter 200 Mode 4 Input Capture Plus Timer Input Capture Plus Timer Mode Timer Interrupts Timer I/O FunctionsTaen Tben Timer Registers Reload/Capture a Register Tcra Timer Mode Control Register TctrlReload/Capture B Register Tcrb Timer Interrupt Control Register Tictl Timer Interrupt Clear Register Ticlr VTU Functional Description Versatile Timer Unit VTU206 Dual 8-bit PWM Mode VTU PWM Generation VTU 16-bit PWM Mode Dual 16-Bit Capture Mode 208 VTU Dual 16-bit Capture Mode Low Power Mode ISE Mode operation VTU Registers Mode Control Register ModeVTU Registers Name Address Description CxEDG Capture Counter Reset Interrupt Control Register Intctl Interrupt Pending Register Intpnd Clock Prescaler Register 1 CLK1PSClock Prescaler Register 2 CLK2PS Counter Register n COUNTx CNTxDuty Cycle/Capture Register n DTYCAPx Period/Capture Register n PERCAPx Bluetooth LLC Registers Register Map Register Name Size Address Access Value After Comments Type USB Node Registers EPC1 TXC1EPC2 EPC4 Can Module Message Buffers Can Registers DMA Controller Bus Interface Unit Flash Program Memory Interface System ConfigurationFlash Data Memory Interface Triple Clock + Reset CVSD/PCM Converter Multi-Input Wake-Up General-Purpose I/O Ports Register Name Size Address Comments Type Advanced Audio Interface Interrupt Control Unit UART0 UART1 UART2 UART3 Multi-Function Timer ACCESS.busTiming and Watchdog Versatile Timer Unit ADC RNG RngcstRngd Word FF F284h Register Bit Fields USB Setup Toggle Rxlast Rcount RXC0 IGN Ignout Rxen Setup EPC1Nakev OUT Nakmsk Fwev RXWARN31 Fwmsk RXWARN31 Can Control Status Memory Registers Dmac System Configuration Registers BIUTBI Register Flash Flash Data Memory CVSD/PCM CLK3RES PMM Register MIWU16Gpio Registers AAI ICU Registers Uart ACB Registers MWSPI16MFT16 VTU Rngcst ImskRngd Rngdivh Electrical Characteristics Symbol Parameter Conditions Min Max UnitsAbsolute Maximum Ratings TBD IOOff Symbol Parameter Conditions Min Typ Max Units INLLSB DNL Flash Memory ON-CHIP Programming Output Signal Levels Clock and Reset TimingReset and NMI Input Signals TRI-STATE NMI Signal Timing Clock Timing Uart Output Signals Uart Timing Port Output Signals 30.9 I/O Port Timing AAI Output Signals Advanced Audio Interface AAI Timing Transmit Timing, Short Frame Sync Receive Timing, Long Frame Sync MICROWIRE/SPI Timing Microwire/SPI Signals Symbol Description Reference Min nsMicrowire/SPI Input Signals Microwire/SPI Output Signals Normal Mode After FE on Microwire Data Out ValidAlternate Mode After RE On MSK Propagation Time 254 255 Microwire Transaction Timing, Alternate Mode, Scidl = 256 257 ACCESS.BUS Timing ACCESS.bus Output Signals 259 ACB Data Timing 260 USB Port AC Characteristics MULTI-FUNCTION Timer MFT Timing Versatile Timing Unit VTU Timing TIOx Input High Time Rising Edge RE on CLKTIOx Input Low Time RE on CLK 262 External Bus Output Signals External BUS Timing Early Write Between Normal Read Cycles No Wait States 264 265 Consecutive Normal Read Cycles Burst, No Wait States 266 267 Early Write Between Fast Read Cycles 268 Pin Assignments LQFP-128 PackagePWR X1CKO X1CKI Reset TMS Avcc PWR Adgnd Advcc UvccX2CKI X2CKO ENV2 SDA ADC0 TSX+ PE0 RXD0 Gpio PE1 TXD0 PE2 RTS PE3 CTS PE4 CKX/TB PE5 SRFS/NMIPF0 MSK/TIO1 PF1 MDIDO/TIO2 LQFP-144 Package 272 SCL SDA ADC0 TSX+ ADC4 MUXOUT0ADC5 MUXOUT1 ADC7 Adcin Pin Name Alternate Functions Pin Number Type A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12A11 A10 Revision History Revision HistoryDate Major Changes From Previous Version Physical Dimensions millimeters unless otherwise noted LQFP-128 Package LQFP-144 Package Life Support Policy Form when properly used in accordance with instructionsBanned Substance Compliance

CP3BT26

Figure 135. Early Write Between Fast Read Cycles

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