Uart Mode Select Register 1 UnMDSL1 | National CP3BT26 manual

CP3BT26

UPEN	The Parity Enable bit enables or disables par-
	ity generation and parity checking. When the
	UART is configured to transmit nine data bits
	per frame, there is no parity bit and the Un-
	PEN bit is ignored.
	0	– Parity generation and checking disabled.
	1	– Parity generation and checking enabled.

22.3.6UART Mode Select Register 1 (UnMDSL1)

The UnMDSL1 register is a byte-wide, read/write register that selects the clock source, synchronization mode, atten- tion mode, and line break generation. This register is cleared at reset. The register format is shown below.

7	6		5	4		3		2	1		0
URTS	UFCE	UERD		UETD	UCKS		UBRK		UATN	UMOD

UMOD	The Mode bit selects between synchronous
	and asynchronous mode. Synchronous mode
	is only available for the UART0 module.
	0		– Asynchronous mode.
	1		– Synchronous mode.
UATN	The Attention Mode bit is used to enable At-
	tention mode. When set, this bit selects the at-
	tention mode of operation for the UART. When
	clear, the attention mode is disabled. The
	hardware clears this bit after an address
	frame is received. An address frame is a 9-bit
	character with a 1 in the ninth bit position.
	0		– Attention mode disabled.
	1		– Attention mode enabled.
UBRK	The Force Transmission Break bit is used to
	force the TXD output low. Setting this bit to 1
	causes the TXD pin to go low. TXD remains
	low until the UBRK bit is cleared by software.
	0		– Normal operation.
	1		– TXD pin forced low.
UCKS	The Synchronous Clock Source bit controls
	the clock source when the UART operates in
	the synchronous mode (UMOD = 1). This
	functionality is only available for the UART0
	module. If the UCKS bit is set, the UART op-
	erates from an external clock provided on the
	CKX pin. If the UCKS bit is clear, the UART
	operates from the baud rate clock produced
	by the UART on the CKX pin. This bit is ig-
	nored when the UART operates in the asyn-
	chronous mode.
	0		– Internal baud rate clock is used.
	1		– External clock is used.
UETD	The Enable Transmit DMA bit controls wheth-
	er DMA is used for UART transmit operations.
	Enabling transmit DMA automatically disables
	transmit interrupts, without regard to the state
	of the UETI bit.
	0		– Transmit DMA disabled.
	1		– Transmit DMA enabled.


UERD	The Enable Receive DMA bit controls whether
	DMA is used for UART receive operations.
	Enabling receive DMA automatically disables
	receive interrupts, without regard to the state
	of the UERI bit. Receive error interrupts are
	unaffected by the UERD bit.
	0	– Receive DMA disabled.
	1	– Receive DMA enabled.
UFCE	The Flow Control Enable bit controls whether
	flow control interrupts are enabled.
	0	– Flow control interrupts disabled.
	1	– Flow control interrupts enabled.
URTS	The Ready To Send bit directly controls the
	state of the					RTS	output.
	0	–		RTS	output is high.
	1	–	RTS		output is low.

22.3.7UART Status Register (UnSTAT)

The UnSTAT register is a byte-wide, read-only register that contains the receive and transmit status bits. This register is cleared upon reset. Any attempt by software to write to this register is ignored. The register format is shown below.


7	6	5		4	3		2	1		0
Res.	UXMIP		URB9	UBKD	UERR	UDOE		UFE	UPE

UPE	The Parity Error bit indicates whether a parity
	error is detected within a received character.
	This bit is automatically cleared by the hard-
	ware when the UnSTAT register is read.
	0	– No parity error occurred.
	1	– Parity error occurred.
UFE	The Framing Error bit indicates whether the
	UART fails to receive a valid stop bit at the end
	of a frame. This bit is automatically cleared by
	the hardware when the UnSTAT register is
	read.
	0	– No framing error occurred.
	1	– Framing error occurred.
UDOE	The Data Overrun Error bit is set when a new
	character is received and transferred to the
	UnRBUF register before software has read
	the previous character from the UnRBUF reg-
	ister. This bit is automatically cleared by the
	hardware when the UnSTAT register is read.
	0	– No receive overrun error occurred.
	1	– Receive overrun error occurred.
UERR	The Error Status bit indicates when a parity,
	framing, or overrun error occurs (any time that
	the UPE, UFE, or UDOE bit is set). It is auto-
	matically cleared by the hardware when the
	UPE, UFE, and UDOE bits are all 0.
	0	– No receive error occurred.
	1	– Receive error occurred.

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National CP3BT26 manual Uart Mode Select Register 1 UnMDSL1, Uart Status Register UnSTAT

Contents

MAY Block DiagramGeneral Description National Semiconductor Corporation Table of Contents Features Device Overview Quad Uart Bluetooth LLCCan Interface Advanced Audio Interface MULTI-FUNCTION Timer MICROWIRE/SPIACCESS.BUS Interface Versatile Timer Unit Serial Debug Interface Power ManagementDMA Controller Development Support LQFP-128 Signal DescriptionsCP3BT26 LQFP-144 Bbclk ResetX1CKI X1CKO Name Pins Primary Function Alternate Alternate Function PG5 PG4Sdat PG6 X1CKI WR1 SelioWR0 CTS PE4 SLE Dedicated Address Registers CPU ArchitectureGENERAL-PURPOSE Registers 12 11 Reserved Processor Status Register PSRInterrupt Base Register Intbase No carry or borrow occurred Carry or borrow occurred Mode for the CR16B large model. Configuration Register CFGWhen the IDT has 16-bit entries, and all ex Is held in the Intbase register, which is not Loadw 12R5, R6 Addressing ModesAddb R1, R2 Stacks Instruction SET Instruction Set Summary Mnemonic Operands Description Tbit AshudLshd LPR POP RetxPush Popret NOP StormpEiwait Wait IN/A MemoryOperating Environment BIU Control Registers BUS Interface Unit BIUBUS Cycles Empty 2 I/O Zone Configuration Register Iocfg Static Zone 0 Configuration Register SZCFG0 WBR RBE Hold Wait Ipst Static Zone 1 Configuration Register SZCFG1Static Zone 2 Configuration Register SZCFG2 Flash Program/Data Memory Access to PeripheralsWait and Hold States RAM Memory System Configuration Registers Name Address Description System Configuration RegistersModule Configuration Register Mcfg Software Reset Register Swreset Module Status Register Mstat Flash Memory Organization Flash MemoryFlash Memory Protection Flash Memory Operations Information Block Module Erase Main Block Page EraseMain Block Module Erase Main Block Write Area BootInformation Block Words Flash Memory Interface Registers CPU Reset BehaviorBoot Area Start-Up Operation Empty Ispe Flash Memory Information Block Data Register Flash Memory 0 Write Enable Register FM0WER/FSM0WERFlash Memory 1 Write Enable Register FM1WER FMIBDR/FSMIBDR Fsmctrl Flash Data Memory 0 Write Enable Register FSM0WERFlash Memory Control Register Fmctrl FMSTART/FSMSTART FsmstatFsmpsr Flash Memory End Time Reload Register FMEND/FSMEND Flash Memory Auto-Read Register 2 FMAR2/ FSMAR2 FMRCV/FSMRCV FSMAR1Flash Memory Auto-Read Register 0 FMAR0/ FSMAR0 Transfer Types DMA ControllerChannel Assignment DMA Channel Assignment Peripheral Trans Register Action Operation Modes DMA Controller Register SET Debug ModeSoftware DMA Request Device B Address Counter Register ADCBn Device a Address Counter Register ADCAnDevice a Address Register ADRAn Device B Address Register ADRBn Block Length Register BLTRn DMA Control Register DMACNTLn VLD DMA Status Register DmastatVLD Chac OVR Maskable Interrupts InterruptsNON-MASKABLE Interrupts Interrupt Controller Registers Non-Maskable Interrupt Status Register Nmistat Interrupt Vector Register IvctExternal NMI Trap Control and Status Register Exnmi Interrupt Status Register 1 ISTAT1 Interrupt Enable and Mask Register 1 IENAM1Interrupt Enable and Mask Register 2 IENAM2 Interrupt Status Register 2 ISTAT2 Maskable Interrupts Assignment IRQ Number Description Maskable Interrupt SourcesNested Interrupts IRQ Number Description Triple Clock and Reset Triple Clock and Reset Module Type External Crystal NetworkCrystal Resonance Frequency Capacitor C1, C2 Capacitance PLL Clock Main ClockSlow Clock Min. Q factor Clock and Reset Registers POWER-ON ResetExternal Reset System Clock MODE20 Power Save Mode Power ManagementActive Mode Module Activity Summary Power Mode Clock Power Management Registers Name Address Description Idle Mode Power Management RegistersHalt Mode Power Management Control Register Pmmcr Hcch DHCHccm OHC Active Mode to Power Save ModeOHC OMC OLC Software-Controlled Transition to Active Mode Entering Idle ModeEntering Halt Mode Wake-Up Transition to Active Mode Multi-Input Wake-Up Module Block Diagram Multi-Input Wake-Up Miwu Channel MULTI-INPUT WAKE-UP RegistersMiwu Sources Multi-Input Wake-Up Registers Name Address Description Wake-Up Enable Register WK0ENA Wake-Up Interrupt Enable Register WK0IENAWake-Up 1 Interrupt Enable Register WK1IENA Wake-Up 1 Edge Detection Register WK1EDG Wake-Up 1 Interrupt Control Register Wake-Up Interrupt Control RegisterWK0ICTL1 WK0ICTL2 WK1ICTL1 WK1ICTL2 Wake-Up 1 Pending Register WK1PND Wake-Up Pending Register WK0PNDWake-Up Pending Clear Register WK0PCL Wake-Up 1 Pending Clear Register WK1PCL Programming Procedures Input/Output Ports Port Registers Port Registers Address Description Port Data Output Register PxDOUT Port Alternate Function Register PxALTPort Data Input Register PxDIN Port Direction Register PxDIR Alternate Function Select Port High Drive Strength Register PxHDRVPort Alternate Function Select Register PxALTS Port Pin PxALTS = OPEN-DRAIN Operation X1CKI/BBCLK Bluetooth ControllerRF Interface Rfdata Sclk Serial InterfaceRfce Sdat Write Operation Serial Interface Write Timing Read Operation Bit, and register address for a read cycle. In the second First part of read cycle driven by CP3BT26. Address is 0Ah 15.3 LMX5251 POWER-UP Sequence 15.4 LMX5252 POWER-UP Sequence Bluetooth Sequencer RAM Bluetooth Sleep ModeBluetooth Global Registers Bluetooth Shared Data RAM Data Path 16.0 12-Bit Analog to Digital ConverterFunctional Description ADC Voltage References OperationADC Clock Generation Pen-Down Detector Touchscreen Driver Configuration Touchscreen Interface RY2 Measuring Pen ForceRX2 RYP ADC Register SET ADC Operation in POWER-SAVING ModesFreeze ADC Registers Name Address Description Muxcfg Touchcfg ADC0/TSX+ ADC1/TSY+ ADC2/TSX ADC3/TSY Clkdiv PrefcfgNrefcfg ADC Start Conversion Register Adcstart ADC Start Conversion Delay Register AdcscdlyADC Conversion Control Register Adccntrl Adcoflw ADC Result Register AdcresltAdcresult Sign RNG Module Block Diagram Random Number Generator RNG Random Number Generator Register SET USB Controller Functional States Endpoint Operation TX Fifo RX Fifo Bidirectional Control Endpoint FIFO0 Operation Transmit Endpoint Fifo Operation TXFIFO1, TXFIFO2, TXFIFO3 USB Controller Registers Name Address Description USB Controller RegistersReceive Endpoint Fifo Operation RXFIFO1, RXFIFO2, RXFIFO3 Main Control Register Mcntrl USB Functional States Node Functional State Register NfsrNFS NFS Alternate Event Register Altev Main Event Register MaevMain Mask Register Mamsk Transmit Mask Register Txmsk Alternate Mask Register AltmskTransmit Event Register Txev NAK Mask Register Nakmsk Receive Event Register Rxev NAK Event Register NakevReceive Mask Register Rxmsk Fifo Warning Mask Register Fwmsk Fifo Warning Event Register FwevFrame Number High Byte Register FNH Dsrc DMA Event Register Dmaev Mirror Register MIR DMA Error Register DmaerrDMA Mask Register Dmamsk DMA Count Register Dmacnt Transmit Status 0 Register TXS0 Transmit Command 0 Register TXC0Endpoint Control 0 Register EPC0 Receive Status 0 Register RXS0 Receive Command 0 Register RXC0Transmit Data 0 Register TXD0 Transmit Status Register n TXSn Receive Data 0 Register RXD0Endpoint Control Register n EPCn Last Transmit Command Register n TXCnTfwl RFF Tfwl Transmit Fifo Warning LimitReceive Status Register n RXSn Bytes Remaining in Fifo Receive Fifo Warning Limit Receive Command Register n RXCn Receive Data Register n RXDTransceiver Interface Rfwl Can Module Can Block Diagram Basic can Concepts Start of Frame SOF Can Frame TypesCan Frame Fields Arbitration Field Cyclic Redundancy Check CRC Data Length Code DLCData Field ACK Field Cyclic Redundancy Check Field CRC Remote FrameData Field Error Frame Error Frame Overload Frame Bit CRC Error Stuff ErrorForm Error Acknowledgment Error Error Passive Error ActiveError Warning Error Counters Synchronization Bit Time LogicCan Bit Time Bit Timing Message Transfer CKI Two 32-bit masks are used to filter unwanted messages Acceptance FilteringExample 1 Acceptance of a Single Identifier From the can bus Gmask and BMASK. shows Receive Structure 120 Writing to Buffer Status Code During Receive ProcedureReceive Timing Rxbusy Buffer Read Routine Bufflock Enabled 122 Transmit Priority Transmit StructureTransmit Scheduling Txpri PRI Interrupts TX Buffer States Time Stamp Counter IRQ IST3 IST2 IST1 IST0 Message Buffer Organization CPU Access to can Registers/MemoryMemory Organization Message Buffer Map Address Register Buffer Status/Control Register Cnstat Can Controller RegistersCan Controller Registers Name Address Description Buffer Status Buffer Status Section of the Cnstat RegisterST3 DIR ST2 ST1 ST0 Busy Storage of Standard Messages Data Length CodingDLC Standard Frame with 8 Data Bytes Address Buffer Register PRI SRR Extended Messages with 8 Data Bytes Address Buffer RegisterCnstat DLC Storage of Remote Messages Frame is received, the contents of these registers will beContents of these registers are ignored. If a remote Extended Remote Frame Address Buffer Register Can Global Configuration Register Cgcr When the Loopback bit is set, all messages Listen Only bit can be used to configureWhen the Ignore Acknowledge bit is set, Dress, as shown in Figure SJW RTR IDE TSEG1TSEG2 Xrtr Basic Mask BM2818 Can Interrupt Enable Register CienBasic Mask Register BMSKB/BMSKX BM170 IRQ Error Field Identifier Can Error Counter Register CanecCan Error Diagnostic Register Cediag EFID30 System START-UP and MULTI-INPUT WAKE-UP Can Timer Register CtmrExternal can Pins Signal Name Type Description External Connection Acceptance Filter Considerations Minimum Clock Frequency Requirements Baud RateBit Time Logic Calculation Examples Remote Frames Usage Hint Audio Interface Modes Audio Interface SignalsAdvanced Audio Interface DMA Support Synchronous ModeNormal Mode 145 BIT Clock Generation Clock ConfigurationFrame Clock Generation Audio Interface Operation Fifo Operation TransmitDMA Operation Receive Data Word Length Frame Sync SignalCommunication Options Audio Control Data Short and Long Frame Sync Pulses 150 IOM-2 ModeLoopback Mode Audio Interface Registers Name Address Description Freeze ModeAudio Interface Registers Audio Receive DMA Register n ARDRn Audio Receive Fifo Register ArfrAudio Transmit Fifo Register Atfr Audio Transmit DMA Register n ATDRn SCS Audio Global Configuration Register AgcrSlots per Mode Frame FSL Txeic Txic Rxeic Rxic Rxie Audio Interrupt Status and Control Register AiscrTxeip Txip Rxeip Rxip Txeie Txie Rxeie Rxie Txeip Audio Receive Status and Control Register Arscr Rxsa Bit Slots EnabledRxdsa Bit Slots Enabled For DMA Audio Transmit Status and Control Register Atscr Txsa Bit Slots EnabledTxdsa Bit Slots Enabled For DMA RMD Audio Clock Control Register AccrAudio DMA Control Register Admacr DMA Request Condition PCM Conversions CVSD/PCM Conversion ModuleOperation Cvsd to PCM Conversion Cvsd ConversionPCM to Cvsd Conversion Interrupt Generation CVSD/PCM Converter Registers Linearout Cvsd Status Register Cvstat Uart Operation Uart ModulesFunctional Overview Uart Block Diagram Uart Asynchronous Communication Diagnostic Mode Frame Format Selection Prescaler Factors Prescaler Factor Break Generation and Detection Parity Generation and Detection Uart Registers Uart Registers Name Address Description Uart Transmit Data Buffer UnTBUF Uart Baud Rate Divisor UnBAUDUart Receive Data Buffer UnRBUF Uart Frame Select Register UnFRS Uart Mode Select Register 1 UnMDSL1 Uart Status Register UnSTAT UOVSR30 Uart Interrupt Control Register UnICTRLUart Oversample Rate Register UnOVR Oversampling Rate Uart Sample Position Register UnSPOS Uart Mode Select Register 2 UnMDSL2Baud Rate Calculations Oversampling Rate Sample Position 173 174 Microwire Interface Microwire/SPI InterfaceMicrowire Operation Shifting Writing Clocking Modes Master Mode Normal Mode Scidl = MWCTRL1 Slave ModeMicrowire Interrupt Trigger Condition Status Enable Bit Microwire Interface Registers Mwen Scdv Microwire Status Register MwstatSCM OVR RBF BSY Data Transactions ACCESS.bus InterfaceACB Protocol Overview Start and Stop Arbitration on the Bus Acknowledge CycleAddressing Transfer Formats ACB Functional Description Slave Mode Master Error DetectionsBus Idle Error Recovery Slave Error Detections ACCESS.BUS Interface Registers ACB Control Status Register Acbcst Start TgsclACB Control Register 1 ACBCTL1 Stop ACB Control Register 2 ACBCTL2 ACB Control Register 3 ACBCTL3 Saen Addr Usage HintsACB Own Address Register 1 ACBADDR1 Saen Avoiding Bus Error During Write Transaction 190 191 TWM Structure Timer T0 OperationTiming and Watchdog Module TWM Registers Power Save Mode OperationWatchdog Operation Register Locking Mdiv T0IN TWMT0 Control and Status Register T0CSR Watchdog Programming ProcedureWatchdog Service Data Match Register Wdsdm Watchdog Count Register Wdcnt Clock Source Block Multi-Function TimerTimer Structure 196 Limitations in Low-Power Modes Timer Operating ModesPulse Accumulate Mode Counter Clock Source Select Mode 1 Processor-Independent PWM 198 Mode 2 Dual Input Capture Dual-Input Capture Mode Mode 3 Dual Independent Timer/Counter 200 Mode 4 Input Capture Plus Timer Input Capture Plus Timer Mode Taen Timer InterruptsTimer I/O Functions Tben Timer Registers Reload/Capture B Register Tcrb Timer Mode Control Register TctrlReload/Capture a Register Tcra Timer Interrupt Control Register Tictl Timer Interrupt Clear Register Ticlr 206 Versatile Timer Unit VTUVTU Functional Description Dual 8-bit PWM Mode VTU PWM Generation VTU 16-bit PWM Mode Dual 16-Bit Capture Mode 208 VTU Dual 16-bit Capture Mode Low Power Mode ISE Mode operation VTU Registers Name Address Description Mode Control Register ModeVTU Registers CxEDG Capture Counter Reset Interrupt Control Register Intctl Clock Prescaler Register 2 CLK2PS Clock Prescaler Register 1 CLK1PSInterrupt Pending Register Intpnd Duty Cycle/Capture Register n DTYCAPx Counter Register n COUNTxCNTx Period/Capture Register n PERCAPx Bluetooth LLC Registers Register Map Register Name Size Address Access Value After Comments Type USB Node Registers EPC2 EPC1TXC1 EPC4 Can Module Message Buffers Can Registers DMA Controller Bus Interface Unit Flash Data Memory Interface System ConfigurationFlash Program Memory Interface Triple Clock + Reset CVSD/PCM Converter Multi-Input Wake-Up General-Purpose I/O Ports Register Name Size Address Comments Type Advanced Audio Interface Interrupt Control Unit UART0 UART1 UART2 UART3 Timing and Watchdog ACCESS.busMulti-Function Timer Versatile Timer Unit ADC Rngd RNGRngcst Word FF F284h Register Bit Fields USB Nakev OUT Nakmsk Fwev RXWARN31 Setup Toggle Rxlast Rcount RXC0IGN Ignout Rxen Setup EPC1 Fwmsk RXWARN31 Can Control Status Memory Registers Dmac TBI Register System Configuration RegistersBIU Flash Flash Data Memory CVSD/PCM CLK3RES Gpio Registers PMM RegisterMIWU16 AAI ICU Registers Uart MFT16 MWSPI16ACB Registers VTU Rngd RngcstImsk Rngdivh Absolute Maximum Ratings Electrical CharacteristicsSymbol Parameter Conditions Min Max Units TBD IOOff LSB Symbol Parameter Conditions Min Typ Max UnitsINL DNL Flash Memory ON-CHIP Programming Reset and NMI Input Signals Output Signal LevelsClock and Reset Timing TRI-STATE NMI Signal Timing Clock Timing Uart Output Signals Uart Timing Port Output Signals 30.9 I/O Port Timing AAI Output Signals Advanced Audio Interface AAI Timing Transmit Timing, Short Frame Sync Receive Timing, Long Frame Sync Microwire/SPI Input Signals MICROWIRE/SPI TimingMicrowire/SPI Signals Symbol Description Reference Min ns Microwire/SPI Output Signals Alternate Mode After RE On MSK Propagation Time Normal Mode After FE onMicrowire Data Out Valid 254 255 Microwire Transaction Timing, Alternate Mode, Scidl = 256 257 ACCESS.BUS Timing ACCESS.bus Output Signals 259 ACB Data Timing 260 USB Port AC Characteristics MULTI-FUNCTION Timer MFT Timing TIOx Input Low Time RE on CLK Versatile Timing Unit VTU TimingTIOx Input High Time Rising Edge RE on CLK 262 External Bus Output Signals External BUS Timing Early Write Between Normal Read Cycles No Wait States 264 265 Consecutive Normal Read Cycles Burst, No Wait States 266 267 Early Write Between Fast Read Cycles 268 PWR Pin AssignmentsLQFP-128 Package X1CKO X1CKI X2CKI X2CKO ENV2 Reset TMSAvcc PWR Adgnd Advcc Uvcc SDA ADC0 TSX+ PF0 MSK/TIO1 PE0 RXD0 Gpio PE1 TXD0 PE2 RTS PE3 CTS PE4 CKX/TB PE5SRFS/NMI PF1 MDIDO/TIO2 LQFP-144 Package 272 ADC5 MUXOUT1 SCL SDA ADC0 TSX+ADC4 MUXOUT0 ADC7 Adcin Pin Name Alternate Functions Pin Number Type A11 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13A12 A10 Date Major Changes From Previous Version Revision HistoryRevision History Physical Dimensions millimeters unless otherwise noted LQFP-128 Package LQFP-144 Package Banned Substance Compliance Form when properly used in accordance with instructionsLife Support Policy