Freescale Semiconductor MPC860T Fifo Transmit Start Register Xfstart, Xwmrk Field Descriptions

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

for the system bus. Setting the watermark to a high value lowers the risk of a transmit FIFO underrun due to system bus contention.

Bits	0	1	2	3	4	5	6		7		8	9	10	11	12	13	14	15
Field										Ñ
Reset							0000_0000_0000_0000
R/W									Read/write
Addr									0xED0
Bits	16	17	18	19	20	21	22		23		24	25	26	27	28	29	30	31
Field								Ñ									X_WMRK
Reset							0000_0000_0000_0000
R/W									Read/write
Addr									0xEDC

Figure 6-17. X_WMRK Register

Table 6-19 bit Þeld descriptions for X_WMRK.

		Table 6-19. X_WMRK Field Descriptions
Bits	Name	Description
0Ð29	Ñ	Reserved. Should be written to zero by the host processor.
30Ð31	X_WMRK	Transmit FIFO watermark. Frame transmission begins when the number of bytes selected by
		this Þeld have been written into the transmit FIFO or if an end of frame has been written to the
		FIFO or if the FIFO is full before the selected number of bytes have been written.
		0x 64 bytes written to the transmit FIFO

10128 bytes written to the transmit FIFO

11192 bytes written to the transmit FIFO

6.2.18FIFO Transmit Start Register (X_FSTART)

The X_FSTART register, shown in Figure 6-18, can be programmed by the user to indicate the starting address of the transmit FIFO. X_FSTART is reset to the Þrst available RAM address. The speciÞc reset value is microcode-dependent. Users do not normally need to program X_FSTART. If users want to reserve RAM locations for other purposes, X_FSTART should never be set to value less than reset value.

MOTOROLAChapter 6.Programming Model6-17

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