Describes Xdesstart Þelds | Freescale Semiconductor MPC860T specs

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Bits	0	1	2	3	4	5		6		7		8		9	10	11	12	13	14		15

Field									X_DES_START

Reset										UndeÞned

R/W										Read/write

Addr										0xE14

Bits	16	17	18	19	20	21		22		23		24		25	26	27	28	29	30		31

Field							X_DES_START													00

Reset										UndeÞned

R/W										Read/write

Addr										0xE16

Figure 6-6. X_DES_START Register

Table 6-7 describes X_DES_START Þelds.

Table 6-7. X_DES_START Field Descriptions

Bits	Name	Description

0Ð29	X_DES_START	Pointer to start of TxBD queue.

30Ð31	Ñ	Reserved. Should be written to zero by the host processor.

6.2.7 Receive Buffer Size Register (R_BUFF_SIZE)

The R_BUFF_SIZE register, shown in Figure 6-7, is like the MRBLR register used by other protocols. It speciÞes the maximum size of all receive buffers. It does not reset and must be initialized by the user. Because the maximum frame is 2047 bytes, only bits 21Ð27 are used. This value should take into consideration that the receive CRC is always written into the last receive buffer. To support frame lengths up to 1520 bytes, R_BUFF_SIZE must be at least 0x0000_05F0. To ensure that R_BUFF_SIZE is a multiple of 16, bits 28Ð31 are forced to zeros. Using buffers smaller than the recommended minimum 256 bytes increases the risk of receive FIFO overßow due to the overhead of opening and closing buffers.

6-6MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Freescale Semiconductor MPC860T user manual Receive Buffer Size Register Rbuffsize, Describes Xdesstart Þelds

Contents

MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, Inc Motorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title Number Viii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Lists signiÞcant changes between revisions of this document Document Revision HistoryOverview Document Revision History Features Comparison with the MPC860 1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU Glueless System Design SIU Interrupt ConÞguration Inc Name Pin Description Signal DescriptionsFEC Signal Descriptions RXD3 L1RSYNCBMiimdc Miitxer REJECT4 REJECT3MIITXD2 MIITXD1 Freescale Semiconductor, Inc Transceiver Connection MII SignalsSignal Description FEC Signal Name This chapter discusses the operation of the FEC TXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission RXD0 FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Hash Table Algorithm Rcntrlprom = Inter-Packet Gap Time Collision Handling Reception Errors Ethernet Error-Handling ProcedureTransmission Errors Internal and External Loopback Reception Errors Chapter Parallel I/O Ports Port D Pin Functions Port D Registers Enabling MII ModeSignal Function Shows the port D pin assignments Sdma Registers CLK FRZ Faid RAID Describes Sdcr ÞeldsSdcr Field Descriptions Bits FEC Parameter RAM Memory Map Parameter RAMBrießy describes each enter in the FEC parameter RAM Address Name Description Section RAM Perfect Match Address Low Register Addrlow Describes the Addrlow Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrhigh Þelds Hashtablehigh Field Descriptions RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashhigh Describes Hashtablelow Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Rdesstart Þelds Xdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Describes Rbuffsize Þelds Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Rbuffsize Field Descriptions Ecntrl Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Fecpinmux 10. IEVENT/IMASK Field Descriptions Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame Hberr 11. Ivec Field Descriptions RxBD Active Register Rdesactive11 describes Ivec Þelds Ilevel 12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14 describes Miidata Þelds 14. Miidata Field Descriptions 15. Miispeed Field Descriptions MII Speed Control Register Miispeed15 describes Miispeed Þelds Dispreamble Miispeed 16. Programming Examples for Miispeed Register Fifo Receive Bound Register Rbound17 describes Rbound Þelds 17. Rbound Field Descriptions 18 describes Rñfstart Þelds Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18. Rfstart Field Descriptions 19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk 20. Xfstart Field Descriptions DMA Function Code Register Funcode20 describes Xfstart Þelds DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 21. Funcode Field Descriptions Receive Control Register Rcntrl21 describes Funcode Þelds Descbo 22. Rcntrl Field Descriptions Receive Hash Register Rhash22 describes Rcntrl Þelds Bcrej 24 describes Xcntrl Þelds Transmit Control Register Xcntrl22 describes Rhash Þelds 23. Rhash Field Descriptions Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence 25. Hardware Initialization User Initialization after Asserting Ecntrletheren 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization Step Description Ethernet Receive Buffer Descriptor RxBD 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Step RO1 RO2 Data Length RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 29. Transmit Buffer Descriptor TxBD Field Descriptions Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds TO1 TO2 DEF CSL Xcntrlhbc = Data Freescale Semiconductor, Inc MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk DC Electrical CharacteristicsAC Electrical Characteristics Electrical SpeciÞcations MII Transmit Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing Num Characteristic Min Max Unit Txen Txer MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing CRS, COL Shows the MII serial management channel timing diagram MII Serial Management Channel Timing Following pins are marked as spare on MPC860T Pin Assignments Freescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product