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NEC uPD98502 User Manual

NEC uPD98502 User Manual

595 pages2.97 Mb

4NOTES FOR CMOS DEVICES
- 6PREFACE
- 1212
- 1616
- LIST OF FIGURES (1/5)
- 17LIST OF FIGURES (2/5)
- 1818
- LIST OF FIGURES (3/5)
- 19LIST OF FIGURES (4/5)
- 2020
- LIST OF FIGURES (5/5)
- 21LIST OF TABLES (1/2)
- 2222
- LIST OF TABLES (2/2)
- 23CHAPTER 1 INTRODUCTION
- 1.1 Features
- 1.2 Ordering Information
- 24
- 1.3 System Configuration
24
- - PD98502
    - The
    - PD98502
      - PD98502 System Configuration (a) ADSL MODEM
      - (b) ADSL ROUTER
      - 251.4 Block Diagram (Summary)
      - 2626
      - 1.5 Block Diagram (Detail)
28System Controller
- IBUS
- SysAD BUS
- RS-232C/Micro Wire
29ATM Cell Processor
- IBUS
- UTOPIA2
- 30Ethernet Controller
  - 31SIE EPC
    - IBUS
  - USB CONTROLLER
  - MCONT
    - Rx FIFO
  - USB
  - BUS I/F
    - I/O Buf
    - Tx FIFO
      - 34Pin Name (1/3)
      - 35(2/3)
    - 371.7 Pin Function
      - 381.7.4 System control interface
      - 391.7.5 Memory interface (1/2)
      - 40(2/2)
      - 411.7.6 PCI interface (1/2)
      - 42(2/2)
      - 431.7.7 ATM interface 1.7.7.1 UTOPIA management interface
      - 441.7.7.2 UTOPIA data interface
      - 451.7.8 Ethernet interface 1.7.8.1 Ethernet interface (Channel 1)
      - 461.7.8.2 Ethernet interface (Channel 2)
      - 1.7.9 USB interface
      - 471.7.10 UART interface
      - 1.7.11 Micro Wire interface
      - 1.7.12 Parallel port interface
      - 1.7.13 Boundary scan interface
    - 491.8 I/O Register Map
    - 531.9 Memory Map
    - 54
    - 1.10 Reset Configuration
54
- PD98502
  - 1.11 Interrupts
  - 55System Controller VR4120A
    - 5656
    - 1.12 Clock Control Unit
      - This section describe
    - 57CHAPTER 2 VR4120A
    - 2.1 Overview for VR4120A
      - VR4120A Core
      - System Controller
        64Table 2-1. System Control Coprocessor (CP0) Register Definitions
    - 6666
    - 2.2 MIPS III Instruction Set Summary
    - 8484
    - 2.3 Pipeline
      - 85(Five stages)
      - Current CPU cycle
      - PCycle
        86Table 2-22. Operation in Each Stage of Pipeline (MIPS III)
        95Table 2-24. Pipeline Interlock
        Table 2-25. Description of Pipeline Exception
    - 1012.4 Memory Management System
      - 111Figure 2-30. Kernel Mode Address Space
      - 116PD98502 Physical Address Space
      - 117Used for memory management system Used for exception processing
      - Remark
      - TLB
      - *: Register number
      - 1180
      - 1200
        127Figure 2-46. TLB Address Translation
    - 1292.5 Exception Processing
      - 160Figure 2-61. Common Exception Handling (2/2) (b) Servicing Common Exceptions (Software)
      - Figure 2-63. Cold Reset Exception Handling
      - 163(Hardware)
      - (Software)
        Cold Reset Exception
        Figure 2-64. Soft Reset and NMI Exception Handling
        164(Hardware)
        (Software)
    - 1652.6 Initialization Interface
    - 168168
    - 2.7 Cache Memory
      - 174Figure 2-73. Data Check Flow on Load Operations
      - 175Figure 2-74. Data Check Flow on Store Operations
      - Figure 2-75. Data Check Flow on Index_Invalidate Operations
      - 176Figure 2-76. Data Check Flow on Index_Writeback_Invalidate Operations
      - Figure 2-77. Data Check Flow on Index_Load_Tag Operations
      - 177Figure 2-78. Data Check Flow on Index_Store_Tag Operations
      - Figure 2-79. Data Check Flow on Create_Dirty Operations
      - 178Figure 2-80. Data Check Flow on Hit_Invalidate Operations
      - Figure 2-81. Data Check Flow on Hit_Writeback_Invalidate Operations
      - 179Figure 2-82. Data Check Flow on Fill Operations
      - Figure 2-83. Data Check Flow on Hit_Writeback Operations
      - 180Figure 2-84. Writeback Flow
      - Figure 2-85. Refill Flow
    - 182182
    - 2.8 CPU Core Interrupts
    - 185CHAPTER 3 SYSTEM CONTROLLER 3.1 Overview
      - 3.1.9 System block diagram
      - 187System Controller
        1883.1.10 Data flow diagram
        VR4120A Core to SDRAM IBUS to SDRAM
        MEM
        VR4120A Core to IBUS VR4120A Core to UART
    - 1893.2 Registers
      - 194Remark To clear this register, the VR4120A must read the byte contained the CBERR register.
    - 2013.3 CPU Interface
      - 202Table 3-1. Endian Configuration Table
    - 204204
    - 3.4 Memory Interface
      - 2053.4.3 Memory signal connections
      - PD98502
      - Remark RMSL signal determines boot memory data bus size.
      - SDRAM
      - Flash PROM
      - Table 3-3. External Pin Mapping
      - 207Remark ROM access timing is depended on the system clock frequency.
  - 208Normal ROM Read Cycle
  - FLAS H Me mory W rite Cycle
  - ROM Burst Read Cycle
    - 210Remark Dont set the reserved value to each field in this register.
    - 211
    - 3.4.1.4 Boot ROM signal connections
    - Example (8 MB PROM)
  - 215FLASH/ROM Configuration
    - Example (4 MB FLASH)
  - 218SDRAM Configuration
    - 4 MB
    - 8 MB
    - 16 MB
    - 32 MB
      - 2213.5 IBUS Interface
        222Outline figure of Endian converter
      - 224224
      - 3.6 DSU (Deadmans SW Unit)
      - 226226
      - 3.7 Endian Mode Software Issues
        Figure 3-1. Bit and Byte Order of Endian Modes
        BYTE0 BYTE1 BYTE2 BYTE3
        Data extraction using sequential halfword access
        31 0
        MSB LSB
        BYTE3 BYTE2 BYTE1 BYTE0
        LSB = Least Significant Byte
        MSB = Most Significant Byte
        MSB LSB
        BYTE4 BYTE5 BYTE6 BYTE7
      - 2274 0
      - Big-Endian
      - Little-Endian
        31 0
        Big End Little End
        BYTE7 BYTE6 BYTE5 BYTE4
      - 4 0
        Big End Little End
        Halfword Data Array
        Big-Endian
        Little-Endian
        Data extraction using sequential halfword access
        Word Data Array
        228Little-Endian
        Big-Endian Data extraction using sequential halfword access
        Data extraction using sequential halfword access
        229CHAPTER 4 ATM CELL PROCESSOR 4.1 Overview
    - 230ATM Cell Processor
      - 232UTOPIA
      - VR4120A RISC Processor
        236
        4.2 Memory Space
      - 236SDRAM Space 64 K
        2374.3 Interruption
        238238
        4.4 Registers for ATM Cell Processing
        2474.5 Data Structure
        CHAPTER 4 ATM CELL PROCESSOR
        248Figure 4-9. Tx Buffer Elements
        - Tx buffer directory
        - Tx link pointer
        - Tx buffer descriptor
        - Tx packet descriptor
        250-Tx link pointer
        -Tx buffer descriptor
        251Figure 4-12. Rx Pool Structure
        CHAPTER 4 ATM CELL PROCESSOR
        Figure 4-13. Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/Rx Link Pointer
        252-Rx buffer directory
        -Rx link pointer
        -Rx buffer descriptor
        -Rx pool descriptor
        253-Rx pool descriptor
        254-Rx link pointer
        -Rx buffer descriptor
        2554.6 Initialization
      - 256F/W
        2574.7 Commands
        262262
        4.8 Operations
        Figure 4-24. Work RAM Usage
        263Work RAM (10 Kbytes)
        267(3) Tx VC table Figure 4-28. Tx VC Table
        Fields defined by user Fields used by DMAC
        271(1) Rx VC table Figure 4-32. Receive VC Table
        0
        277CHAPTER 5 ETHERNET CONTROLLER 5.1 Overview
        Transceiver
        Ethernet Controller Block
        IBUS
        PD98502
        278
        2795.2 Registers
        281Table 5-3. Statistics Counter Register Map
        2855.2.2 En_MACC1 (MAC Configuration Register 1)
        2865.2.3 En_MACC2 (MAC Configuration Register 2)
        5.2.4 En_IPGT (Back-to-Back IPG Register)
        5.2.5 En_IPGR (Non Back-to-Back IPG Register)
        2875.2.6 En_CLRT (Collision Register)
        5.2.7 En_LMAX (Maximum Packet Length Register)
        5.2.8 En_RETX (Retry Count Register)
        5.2.9 En_LSA2 (Station Address Register 2)
        5.2.10 En_LSA1 (Station Address Register 1)
        2885.2.11 En_PTVR (Pause Timer Value Read Register)
        5.2.12 En_VLTP (VLAN Type Register)
        5.2.13 En_MIIC (MII Configuration Register)
        5.2.14 En_MCMD (MII Command Register)
        2895.2.15 En_MADR (MII Address Register)
        5.2.16 En_MWTD (MII Write Data Register)
        5.2.17 En_MRDD (MII Read Data Register)
        5.2.18 En_MIND (MII Indicate Register)
        2905.2.19 En_AFR (Address Filtering Register)
        5.2.20 En_HT1 (Hash Table Register 1)
        5.2.21 En_HT2 (Hash Table Register 2)
        2945.2.26 En_TXCR (Transmit Configuration Register)
        2965.2.28 En_TXDPR (Transmit Descriptor Pointer)
        5.2.29 En_RXCR (Receive Configuration Register)
        2985.2.32 En_RXPDR (Receive Pool Descriptor Pointer)
        5.2.33 En_CCR (Configuration Register)
        5.2.34 En_ISR (Interrupt Serves Register)
        300300
        5.3 Operation
        305.
        306Set RCVDP Set RXE
        309CHAPTER 6 USB CONTROLLER 6.1 Overview
        310SIE EPC
        IBUS
        MCONT
        Rx FIFO
        USB
        BUS I/F
        I/O Buf
        Tx FIFO
        USB CONTROLLER
        3116.2 Registers
        3286.2.24 U_TMSA (USB Tx MailBox Start Address Register)
        6.2.25 U_TMBA (USB Tx MailBox Bottom Address Register)
        6.2.26 U_TMRA (USB Tx MailBox Read Address Register)
        3296.2.27 U_TMWA (USB Tx MailBox Write Address Register)
        6.2.28 U_RMSA (USB Rx MailBox Start Address Register)
        6.2.29 U_RMBA (USB Rx MailBox Bottom Address Register)
        6.2.30 U_RMRA (USB Rx MailBox Read Address Register)
        6.2.31 U_RMWA (USB Rx MailBox Write Address Register)
        330
        6.3 USB Attachment Sequence
        330 PD98502
        3316.4 Initialization
        334
        6.5 Data Transmit Function
        334Data Segment
        64 Bytes 64 Bytes 64 Bytes 64 Bytes 40 Bytes
      - 335Tx Packet
        Buffer Directory
        344
        6.6 Data Receive Function
        344Data Segment
        64 Bytes 64 Bytes 64 Bytes 64 Bytes 40 Bytes
        345Buffer Direc tory
        361Buffer Dire ctory
        364364
        6.7 Power Management
        366VR4120A USB Controller
        Host PC
        PD98502
        3676.8 Receiving SOF Packet
        368368
        6.9 Loopback Mode
        6.10 Example of Connection
        369PD98502
        370370
        CHAPTER 7 PCI CONTROLLER 7.1 Overview
        3717.2 Bus Bridge Functions
        3837.3 PCI Power Management Interface
        384PCI-Host PCI Contro ller
        Intern al Contro ller
        385PCI-Host PCI Contr oller
        Internal Contr oller
        386386
        7.4 Functions in Host-mode
        390390
        7.5 Registers
        4017.5.19 P_CONFIG (PCI Configuration Registers) 7.5.19.1 PCI configuration register map
        Note The view from PCI side address is assigned by Register Memory Base Address Register.
        4117.6 Information for Software
        414414
        CHAPTER 8 UART 8.1 Overview
        8.2 UART Block Diagram
        URSDI
        URCLK
        URSDO
        URRTS_B URCTS_B URDTR_B URDSR_B URDCD_B
        INTPR (to VR4120A)
        4158.3 Registers
        417Table 8-1. Correspondence between Baud Rates and Divisors
        424424
        CHAPTER 9 TIMER 9.1 Overview
        9.2 Block Diagram
        4259.3 Registers
        427CHAPTER 10 MICRO WIRE 10.1 Overview
        428428
        10.2 Operations
        42910.3 Registers
        10.3.1 Register map
        10.3.2 ECCR (EEPROM Command Control Register)
        10.3.3 ERDR (EEPROM Read Data Register)
        10.3.4 MACAR1 (MAC Address Register 1)
        10.3.5 MACAR2 (MAC Address Register 2)
        43010.3.6 MACAR3 (MAC Address Register 3)
        431APPENDIX A MIPS III INSTRUCTION SET DETAILS
        A.1 Instruction Notation Conventions
        432Table A-1. CPU Instruction Operation Notations
        433A.2 Load and Store Instructions
        434434
        A.3 Jump and Branch Instructions
436ADD Add ADD
- 437ADDI Add Immediate ADDI
  - ADDI 0 0 1 0 0 0 rt immediate
  - 438
438ADDIU
- g
- ned ADDIU
  - ADDIU 0 0 1 0 0 1 rt immediate
- 439ADDU Add Unsigned ADDU
  - rs
  - 0 0 0 0 0
  - SPECIAL 0 0 0 0 0 0 rt rd 0
  - ADDU 1 0 0 0 0 1
- 440AND And AND
- 441ANDI And Immediate ANDI
  - ANDI 0 0 1 1 0 0 rt immediate
  - 442
442BC0F Branch On Coprocessor 0 False BC0F
- 0 0 0 0 0 offset
- 0 1 0 0 X X
443BC0FL
- p
- rocessor 0 False Likel
  - 0 0 0 1 0 offset
- y
- (
- 1/2
- )
BC0FL
- 0 1 0 0 X X
444BC0FL
- p
- rocessor 0 False Likel
- y
- (
- 2/2
- )
BC0FL
- Opcode Table:
445BC0T Branch On Coprocessor 0 True BC0T
- 0 0 0 0 1 offset
- 0 1 0 0 X X
- 446
446BC0TL Branch On Coprocessor 0 True Likely (1/2) BC0TL
- 0 1 0 0 X X
- BCTL 0 0 0 1 1 offset
447BC0TL Branch On Coprocessor 0 True Likely (2/2) BC0TL
- Opcode Table:
- 448BEQ Branch On Equal BEQ
  - BEQ 0 0 0 1 0 0 rt offset
- 449BEQL Branch On Equal Likely BEQL
  - BEQL 0 1 0 1 0 0 rt offset
- 450BGEZ Branch On Greater Than Or Equal To Zero BGEZ
  - BGEZ 0 0 0 0 1 offset
- 451BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL
  - BGEZAL 1 0 0 0 1 offset
- 452BGEZALL Branch On Greater Than Or Equal To Zero And Link Likely BGEZALL
  - BGEZALL 1 0 0 1 1 offset
- 453BGEZL Branch On Greater Than Or Equal To Zero Likely BGEZL
  - BGEZL 0 0 0 1 1 offset
- 454BGTZ Branch On Greater Than Zero BGTZ
  - BGTZ 0 0 0 1 1 1
- 455BGTZL Branch On Greater Than Zero Likely BGTZL
  - BGTZL 0 1 0 1 1 1
- 456BLEZ Branch On Less Than Or Equal To Zero BLEZ
  - BLEZ
- 457BLEZL Branch On Less Than Or Equal To Zero Likely BLEZL
  - BLEZL 0 1 0 1 1 0
- 458BLTZ Branch On Less Than Zero BLTZ
  - BLTZ
- 459BLTZAL Branch On Less Than Zero And Link BLTZAL
  - BLTZAL 1 0 0 0 0 offset
  - 460
460BLTZALL Branch On Less Than Zero And Link Likely BLTZALL
- REGIMM 0 0 0 0 0 1
- BLTZALL 1 0 0 1 0 offset
- 461BLTZL Branch On Less Than Zero Likely BLTZL
  - BLTZL 0 0 0 1 0 offset
- 462BNE Branch On Not Equal BNE
  - BNE 0 0 0 1 0 1 rt offset
- 463BNEL Branch On Not Equal Likely BNEL
  - BNEL 0 1 0 1 0 1 rt offset
- 464BREAK Breakpoint BREAK
465CACHE Cache (1/4) CACHE
- CACHE 1 0 1 1 1 1 op offset
  - CE
- 466CACHE Cache (2/4) CACHE
- 467CACHE Cache (3/4) CACHE
- 468CACHE Cache (4/4) CACHE
- 469DADD Doubleword Add DADD
  - DADD 1 0 1 1 0 0
- 470DADDI Doubleword Add Immediate DADDI
  - DADDI 0 1 1 0 0 0 rt immediate
- 471DADDIU Doubleword Add Immediate Unsigned DADDIU
  - DADDIU 0 1 1 0 0 1 rt immediate
- 472DADDU Doubleword Add Unsigned DADDU
- 473DDIV Doubleword Divide DDIV
  - DDIV 0 1 1 1 1 0
  - 474
474DDIVU Doubleword Divide Unsigned DDIVU
- 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 rt 0
- DDIVU 0 1 1 1 1 1
- 475DIV Divide DIV
  - DIV 0 1 1 0 1 0
  - 476
476DIVU Divide Unsigned DIVU
- 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 rt 0
- DIVU 0 1 1 0 1 1
477DMACC Doubleword Multiply and Accumulate (1/3) DMACC
- 0 0 0 0 0 0 rt 1
- DMACC 1 0 1 0 0 1
- rd sat us0 0 0
- 478DMACC Doubleword Multiply and Accumulate (2/3) DMACC
- 479DMACC Doubleword Multiply and Accumulate (3/3) DMACC
- 480DMFC0
- 481DMTC0 Doubleword Move To System Control Coprocessor DMTC0
  - DMT 0 0 1 0 1
  - 0 0 0 0 0 0 0 0 0 0 0
  - 0 1 0 0 0 0 rt rd
- 482DMULT Doubleword Multiply DMULT
  - DMULT 0 1 1 1 0 0
- 483DMULTU Doubleword Multiply Unsigned DMULTU
  - DMULTU 0 1 1 1 0 1
- 484DSLL Doubleword Shift Left Logical DSLL
  - 1 1 1 0 0 0
  - 0 0 0 0 0 0 rt rd sa DSLL
- 485DSLLV Doubleword Shift Left Logical Va riable DSLLV
- 486DSLL32 Doubleword Shift Left Logical + 32 DSLL32
  - 1 1 1 1 0 0
  - 0 0 0 0 0 0 rt rd sa DSLL32
- 487DSRA Doubleword Shift Right Arithmetic DSRA
  - 1 1 1 0 1 1
  - 0 0 0 0 0 0 rt rd sa DSRA
- 488DSRAV Doubleword Shift Right Arithmetic Variable DSRAV
  - DSRAV 0 1 0 1 1 1
- 489DSRA32 Doubleword Shift Right Arithmetic + 32 DSRA32
  - 1 1 1 1 1 1
  - 0 0 0 0 0 0 rt rd sa DSRA32
- 490DSRL Doubleword Shift Right Logical DSRL
  - 1 1 1 0 1 0
  - 0 0 0 0 0 0 rt rd sa DSRL
- 491DSRLV Doubleword Shift Right Logical V ariable DSRLV
- 492DSRL32 Doubleword Shift Right Logical + 32 DSRL32
  - 1 1 1 1 1 0
  - 0 0 0 0 0 0 rt rd sa DSRL32
- 493DSUB Doubleword Subtract DSUB
- 494DSUBU Doubleword Subtract Unsigned DSUBU
- 495ERET Exception Return ERET
  - ERET 0 1 1 0 0 0
    - SR1
    - EXL
    - ERL
  - 496HIBERNATE Hibernate HIBERNATE
- 497JJump J
  - J 0 0 0 0 1 0 target
- 498JAL Jump And Link JAL
  - JAL 0 0 0 0 1 1 target
499JALR Jump And Link Register JALR
- 0 0 0 0 0 0
  - not
  - rd
  - rs
- 0 0 0 0 0 0 rd 0
- JALR 0 0 1 0 0 1
- 500
500JALX Jump And Link Exchange JALX
- JALX 011101
- target
- 501JR Jump Register JR
  - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  - JR 0 0 1 0 0 0
- 502LB Load Byte LB
  - LB 1 0 0 0 0 0 rt offset
- 503LBU Load Byte Unsigned LBU
  - LBU 1 0 0 1 0 0 rt offset
- 504LD Load Doubleword LD
  - LD 1 1 0 1 1 1 rt offset
  - 505LDL Load Doubleword Left (1/3) LDL
    - LDL 0 1 1 0 1 0 rt offset
    - LDL $24, 12 ($0)
      - base
      - offset
      - before after
  - 506LDL Load Doubleword Left (2/3) LDL
  - 507LDL Load Doubleword Left (3/3) LDL
    - LDL
      - 508
  - 508LDR Load Doubleword Right (1/3) LDR
    - LDR $24, 5 ($0)
    - LDR 0 1 1 0 1 1 rt offset
  - 509LDR Load Doubleword Right (2/3) LDR
  - 510LDR Load Doubleword Right (3/3) LDR
    - LDR
- 511LH Load Halfword LH
  - LH 1 0 0 0 0 1 rt offset
- 512LHU Load Halfword Unsigned LHU
  - LHU 1 0 0 1 0 1 rt offset
- 513LUI Load Upper Immediate LUI
  - LUI 0 0 1 1 1 1 rt immediate
- 514LW Load Word LW
  - LW 1 0 0 0 1 1 rt offset
  - 515LWL Load Word Left (1/3) LWL
    - LWL 1 0 0 0 1 0 rt offset
      - LWL $24, 4 ($0)
  - 516LWL Load Word Left (2/3) LWL
  - 517LWL Load Word Left (3/3) LWL
    - LWL
      - S
      - 518
  - 518LWR Load Word Right (1/3) LWR
    - LWR $24, 1 ($0)
    - LWR 1 0 0 1 1 0 rt offset
  - 519LWR Load Word Right (2/3) LWR
    - 520LWR Load Word Right (3/3) LWR
      - LWR
        S
  - 521LWU Load Word Unsigned LWU
    - LWU 1 0 1 1 1 1 rt offset
    - 522
522MACC Multiply and Accumulate (1/5) MACC
- 0 0 0 0 0 0 rt 1
- MACC 1 0 1 0 0 0
- rd sat us0 0
- hi
523MACC Multiply and Accumulate (2/5) MACC
537ORI Or Immediate ORI
- ORI 0 0 1 1 0 1 rt immediate
- 538SB Store Byte SB
  - SB 1 0 1 0 0 0 rt offset
- 539SD Store Doubleword SD
  - SD 1 1 1 1 1 1 rt offset
  - 540
540SDL Store Doubleword Left (1/3) SDL
- SDL 1 0 1 1 0 0 rt offset
  - SDL $24, 8 ($0)
- 541SDL Store Doubleword Left (2/3) SDL
- 542SDL Store Doubleword Left (3/3) SDL
  - SDL
543SDR Store Doubleword Right (1/3) SDR
- SDR 1 0 1 1 0 1 rt offset
  - SDR $24, 1 ($0)
544SDR Store Doubleword Right (2/3) SDR
545SDR Store Doubleword Right (3/3) SDR
- SDR
- 546SH Store Halfword SH
  - SH 1 0 1 0 0 1 rt offset
  - 547SLL Shift Left Logical SLL
    - 0 0 0 0 0 0
    - 0 0 0 0 0 0 rt rd sa SLL
    - 0
    - 548
  - 548SLLV Shift Left Logical Variable SLLV
    - 0 0 0 0 0 0 rt rd 0
    - SLLV 0 0 0 1 0 0
- 549SLT Set On Less Than SLT
  - SLT 1 0 1 0 1 0
- 550SLTI Set On Less Than Immediate SLTI
  - SLTI 0 0 1 0 1 0 rt immediate
- 551SLTIU Set On Less Than Immediate Unsigned SLTIU
  - SLTIU 0 0 1 0 1 1 rt immediate
- 552SLTU Set On Less Than Unsigned SLTU
  - SLTU 1 0 1 0 1 1
- 553SRA Shift Right Arithmetic SRA
  - 0 0 0 0 1 1
  - 0 0 0 0 0 0 rt rd sa SRA
  - 554
- 554SRAV Shift Right Arithmetic Variable SRAV
  - SRAV 0 0 0 1 1 1
- 555SRL Shift Right Logical SRL
  - 0 0 0 0 1 0
  - 0 0 0 0 0 0 rt rd sa SRL
- 556SRLV Shift Right Logical Variable SRLV
  - SRLV
    - rs,
    - rt
  - 557STANDBY Standby STANDBY
- 558SUB Subtract SUB
  - SUB 1 0 0 0 1 0
- 559SUBU Subtract Unsigned SUBU
  - SUBU 1 0 0 0 1 1
  - 560SUSPEND Suspend SUSPEND
- 561SW Store Word SW
  - SW 1 0 1 0 1 1 rt offset
  - 562
- 562SWL Store Word Left (1/3) SWL
  - SWL $24, 4 ($0)
  - SWL 1 0 1 0 1 0 rt offset
563SWL Store Word Left (2/3) SWL
564SWL Store Word Left (3/3) SWL
- SWL
- 565SWR Store Word Right (1/3) SWR
  - SWR 1 0 1 1 1 0 rt offset
    - SWR $24, 1 ($0)
566SWR Store Word Right (2/3) SWR
567SWR Store Word Right (3/3) SWR
- SWR
- 568SYNC Synchronize SYNC
  - 569SYSCALL System Call SYSCALL
    - 570
  - 570TEQ Trap If Equal TEQ
    - TEQ 1 1 0 1 0 0
- 571TEQI Trap If Equal Immediate TEQI
  - TEQI 0 1 1 0 0 immediate
    - 32 T: if GPR [rs] = (immediate15)16 || immediate15...0 then
    - 64 T: if GPR [rs] = (immediate15)48 || immediate15...0 then
- 572TGE Trap If Greater Than Or Equal TGE
  - TGE 1 1 0 0 0 0
- 573TGEI Trap If Greater Than Or Equal Immediat e TGEI
  - TGEI 0 1 0 0 0 immediate
    - 32 T: if GPR [rs] > (immediate15)16 || immediate15...0 then
    - 64 T: if GPR [rs] > (immediate15)48 || immediate15...0 then
- 574TGEIU
  - TGEIU 0 1 0 0 1 immediate
    - 32 T: if (0 || GPR [rs]) > (0 || (immediate15)16 || immediate15...0) then
    - 64 T: if (0 || GPR [rs]) > (0 || (immediate15)48 || immediate15...0) then
  - 575TGEU Trap If Greater Than Or Equal Unsigned TGEU
    - TGEU 1 1 0 0 0 1
- 576TLBP Probe TLB For Matching Entry TLBP
  - TLBP 0 0 1 0 0 0
- 577TLBR Read Indexed TLB Entry TLBR
  - TLBR
- 578TLBWI Write Indexed TLB Entry TLBWI
  - TLBWI 0 0 0 0 1 0
- 579TLBWR Write Random TLB Entry TLBWR
  - TLBWR
- 580TLT Trap If Less Than TLT
  - TLT 1 1 0 0 1 0
- 581TLTI Trap If Less Than Immediate TLTI
  - TLTI 0 1 0 1 0 immediate
    - 32 T: if GPR [rs] < (immediate15)16 || immediate15...0 then
    - 64 T: if GPR [rs] < (immediate15)48 || immediate15...0 then
- 582TLTIU Trap If Less Than Immediate Unsigned TLTIU
  - TLTIU 0 1 0 1 1 immediate
    - 32 T: if (0 || GPR [rs]) < (0 || (immediate15)16 || immediate15...0) then
    - 64 T: if (0 || GPR [rs]) < (0 || (immediate15)48 || immediate15...0) then
- 583TLTU Trap If Less Than Unsigned TLTU
  - TLTU 1 1 0 0 1 1
  - 584
  - 584TNE Trap If Not Equal TNE
    - TNE 1 1 0 1 1 0
- 585TNEI Trap If Not Equal Immediate TNEI
  - TNEI 0 1 1 1 0 immediate
    - 32 T: if GPR [rs] (imm ediate15)16 || immediate15...0 then
    - 64 T: if GPR [rs] (imm ediate15)48 || immediate15...0 then
- 586XOR Exclusive Or XOR
- 587XORI Exclusive OR Immediate XORI
  - XORI 0 0 1 1 1 0 rt immediate
  - 588588
  - A.6 CPU Instruction Opcode Bit Encoding
    - Figure A-1 lists the VR4120A Opcode Bit Encoding. Figure A-1. V
  - 590590
  - APPENDIX B VR4120A COPROCESSOR 0 HAZARDS
    - 591Table B-1. VR4120A CPU Coprocessor 0 Hazards
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