Preliminary User’s Manual S15543EJ1V0UM 17
LIST OF FIGURES (2/5)Figure No. Title Page
2-29 Supervisor Mode Address Space................................................................................................................108
2-30 Kernel Mode Address Space.......................................................................................................................111
2-31
µ
PD98502 Physical Address Space............................................................................................................116
2-32 CP0 Registers and TLB...............................................................................................................................117
2-33 Format of a TLB Entry................................................................................................................................. 118
2-34 Index Register..............................................................................................................................................119
2-35 Random Register.........................................................................................................................................119
2-36 EntryLo0 and EntryLo1 Registers................................................................................................................120
2-37 Page Mask Register....................................................................................................................................121
2-38 Positions Indicated by Wired Register.........................................................................................................122
2-39 Wired Register.............................................................................................................................................122
2-40 EntryHi Register...........................................................................................................................................123
2-41 PRId Register..............................................................................................................................................123
2-42 Config Register Format................................................................................................................................124
2-43 LLAddr Register...........................................................................................................................................125
2-44 TagLo Register............................................................................................................................................125
2-45 TagHi Register.............................................................................................................................................125
2-46 TLB Address Translation.............................................................................................................................127
2-47 Context Register Format..............................................................................................................................131
2-48 BadVAddr Register Format..........................................................................................................................132
2-49 Count Register Format................................................................................................................................ 132
2-50 Compare Register Format...........................................................................................................................133
2-51 Status Register Format................................................................................................................................134
2-52 Status Register Diagnostic Status Field.......................................................................................................135
2-53 Cause Register Format................................................................................................................................136
2-54 EPC Register Format...................................................................................................................................138
2-55 WatchLo Register Format............................................................................................................................139
2-56 WatchHi Register Format............................................................................................................................139
2-57 XContext Register Format...........................................................................................................................140
2-58 Parity Error Register Format........................................................................................................................140
2-59 Cache Error Register Format.......................................................................................................................141
2-60 ErrorEPC Register Format...........................................................................................................................141
2-61 Common Exception Handling......................................................................................................................159
2-62 TLB/XTLB Refill Exception Handling...........................................................................................................161
2-63 Cold Reset Exception Handling...................................................................................................................163
2-64 Soft Reset and NMI Exception Handling......................................................................................................164
2-65 Logical Hierarchy of Memory.......................................................................................................................168
2-66 Cache Support.............................................................................................................................................169
2-67 Instruction Cache Line Format.....................................................................................................................170
2-68 Data Cache Line Format..............................................................................................................................170
2-69 Cache Data and Tag Organization..............................................................................................................171
2-70 Data Cache State Diagram..........................................................................................................................173