NEC uPD98502 - page 396

CHAPTER 7 PCI CONTROLLER

396 Preliminary User’s Manual S15543EJ1V0UM

7.5.10 P_IIMR (Internal Bus Interrupt Mask Register)IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bitposition to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is resetto ‘0’, the corresponding bit of the IGSR is masked. If it is set to ‘1’, the corresponding bit is unmasked. When themask bit is reset and the bit in IGSR is set, the PCI Controller sets the interrupt signal to the VR4120A.

R/WBits Field

Internal

bus

PCI

Default Description

31:16 PUINT R R/W 0000H Interrupts which can be defined by the system the chip is used.

If ‘1’ is written to this field from internal bus side, an interrupt to

PCI-Host is asserted.

15:11 Reserved - - 0H Hardwired to ‘0H’

10 IPREQ R R 0 The transition of PPMI Power state issued.

‘1’ indicates that the VR4120A issues the transition of power state

of The PCI Controller.

9 SWRDN R/W R 0 Software Reset done.

‘1’ indicates that the software reset has been done.

8 DPERR R R 0 Detected PCI Parity Error.

‘1’ indicates that the PCI Controller has detected a parity error on

PCI bus.

7 SSERR R R 0 Signaled SE RR#.

‘1’ indicates that the PCI Controller has asserted SERR_B.

6 RMABT R R 0 Received Master Abort.

‘1’ indicates that the PCI Controller has received Master Abort as

master.

5 RTABT R R 0 Received Target Abort.

‘1’ indicates that the PCI Controller has received Target Abort as

master.

4 STABT R R 0 Signaled Target Abort.

‘1’ indicates that the PCI Controller has executed Target Abort as

target.

3 PFDSC R R 0 PCI FIFO discarded.

‘1’ indicates that the PCI Controller has discarded the data for

read-delayed-transaction in FIFO, because the same issue has

not been repeated within 215 clock.

2 RTYTE R R 0 Retry Timer Expired.

‘1’ indicates that Retry Timer has expired and the PCI Controller

abandons the retry-access. See 7.2.3.1 (5).

1 PRBER R R 0 Internal bus Error in read transact ion

‘1’ indicates that the PCI Controller has received Bus Error on

internal bus during read transaction as master.

0 PWBER R R 0 Internal bus Error in write transaction

‘1’ indicates that the PCI Controller has received Bus Error on

internal bus during write transaction as master.

Contents

Main Page Page NOTES FOR CMOS DEVICES Page PREFACE Page Page Page Page Page 12 Page Page Page 16 LIST OF FIGURES (1/5) LIST OF FIGURES (2/5) 18 LIST OF FIGURES (3/5) LIST OF FIGURES (4/5) 20 LIST OF FIGURES (5/5) LIST OF TABLES (1/2) 22 LIST OF TABLES (2/2) CHAPTER 1 INTRODUCTION 1.1 Features 1.2 Ordering Information 24 1.3 System Configuration 1.4 Block Diagram (Summary) 26 1.5 Block Diagram (Detail) Page System Controller IBUS SysAD BUS RS-232C/Micro Wire ATM Cell Processor IBUS UTOPIA2 Ethernet Controller SIE EPC IBUS USB CONTROLLER MCONT Rx FIFO Page Page Pin Name (1/3) (2/3) Page 1.7 Pin Function 1.7.4 System control interface 1.7.5 Memory interface (1/2) (2/2) 1.7.6 PCI interface (1/2) (2/2) 1.7.7 ATM interface 1.7.7.1 UTOPIA management interface 1.7.7.2 UTOPIA data interface 1.7.8 Ethernet interface 1.7.8.1 Ethernet interface (Channel 1) 1.7.8.2 Ethernet interface (Channel 2) 1.7.9 USB interface 1.7.10 UART interface 1.7.11 Micro Wire interface 1.7.12 Parallel port interface 1.7.13 Boundary scan interface Page 1.8 I/O Register Map Page Page Page 1.9 Memory Map 54 1.10 Reset Configuration PD98502 1.11 Interrupts System Controller VR4120A 56 1.12 Clock Control Unit This section describe CHAPTER 2 VR4120A 2.1 Overview for VR4120A VR4120A Core System Controller Page Page Page Page Page Page Table 2-1. System Control Coprocessor (CP0) Register Definitions Page 66 2.2 MIPS III Instruction Set Summary Page Table 2-3. Byte Specification Related to Load and Store Instructions Table 2-4. Load/Store Instruction Table 2-5. Load/Store Instruction (Extended ISA) Page Table 2-7. ALU Immediate Instruction (Extended ISA) Table 2-8. Three-Operand Type Instruction Table 2-9. Three-Operand Type Instruction (Extended ISA) Table 2-10. Shift Instruction Table 2-11. Shift Instruction (Extended ISA) Table 2-12. Multiply/Divide Instructions Table 2-13. Multiply/Divide Instructions (Extended ISA) Page Page Page Table 2-18. Branch Instructions (Extended ISA) rs Table 2-20. Special Instructions (Extended ISA) (1/2) Table 2-20. Special Instructions (Extended ISA) (2/2) Table 2-21. System Control Coprocessor (CP0) Instructions (2/2) base 84 2.3 Pipeline (Five stages) Current CPU cycle PCycle Table 2-22. Operation in Each Stage of Pipeline (MIPS III) Page Page Page Page Page Page Page Page Table 2-24. Pipeline Interlock Table 2-25. Description of Pipeline Exception Page Page Page Page Page 2.4 Memory Management System Page Page Page Page Page Page Page Page Page Figure 2-30. Kernel Mode Address Space Page Page Page Page PD98502 Physical Address Space Used for memory management system Used for exception processing Remark TLB *: Register number 0 Page 0 Page Page Page Page Page Page Figure 2-46. TLB Address Translation Page 2.5 Exception Processing Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Figure 2-61. Common Exception Handling (2/2) (b) Servicing Common Exceptions (Software) Page Page Figure 2-63. Cold Reset Exception Handling (Hardware) (Software) Cold Reset Exception Figure 2-64. Soft Reset and NMI Exception Handling (Hardware) (Software) 2.6 Initialization Interface Page Page 168 2.7 Cache Memory Page Page Page Page Page Figure 2-73. Data Check Flow on Load Operations Figure 2-74. Data Check Flow on Store Operations Figure 2-75. Data Check Flow on Index_Invalidate Operations Figure 2-76. Data Check Flow on Index_Writeback_Invalidate Operations Figure 2-77. Data Check Flow on Index_Load_Tag Operations Figure 2-78. Data Check Flow on Index_Store_Tag Operations Figure 2-79. Data Check Flow on Create_Dirty Operations Figure 2-80. Data Check Flow on Hit_Invalidate Operations Figure 2-81. Data Check Flow on Hit_Writeback_Invalidate Operations Figure 2-82. Data Check Flow on Fill Operations Figure 2-83. Data Check Flow on Hit_Writeback Operations Figure 2-84. Writeback Flow Figure 2-85. Refill Flow Page 182 2.8 CPU Core Interrupts Page Page CHAPTER 3 SYSTEM CONTROLLER 3.1 Overview Page 3.1.9 System block diagram System Controller 3.1.10 Data flow diagram VR4120A Core to SDRAM IBUS to SDRAM MEM VR4120A Core to IBUS VR4120A Core to UART 3.2 Registers Page Page Page Page Remark To clear this register, the VR4120A must read the byte contained the CBERR register. Page Page Page Page Page Page 3.3 CPU Interface Table 3-1. Endian Configuration Table Page 204 3.4 Memory Interface 3.4.3 Memory signal connections PD98502 Remark RMSL signal determines boot memory data bus size. SDRAM Flash PROM Page Remark ROM access timing is depended on the system clock frequency. Normal ROM Read Cycle FLAS H Me mory W rite Cycle ROM Burst Read Cycle Page Remark Dont set the reserved value to each field in this register. Page Page Page Page 3.4.1.4 Boot ROM signal connections Example (8 MB PROM) FLASH/ROM Configuration Example (4 MB FLASH) Page Page SDRAM Configuration 4 MB 8 MB 16 MB 32 MB Page Page 3.5 IBUS Interface Outline figure of Endian converter Page 224 3.6 DSU (Deadmans SW Unit) Page 226 3.7 Endian Mode Software Issues Figure 3-1. Bit and Byte Order of Endian Modes BYTE0 BYTE1 BYTE2 BYTE3 Data extraction using sequential halfword access 4 0 Big-Endian Little-Endian 31 0 Big End Little End 4 0 Big End Little End Halfword Data Array Big-Endian Little-Endian Little-Endian Big-Endian Data extraction using sequential halfword access Data extraction using sequential halfword access CHAPTER 4 ATM CELL PROCESSOR 4.1 Overview ATM Cell Processor Page UTOPIA VR4120A RISC Processor Page Page Page 236 4.2 Memory Space SDRAM Space 64 K 4.3 Interruption 238 4.4 Registers for ATM Cell Processing Page Page Page Page Page Page Page Page 4.5 Data Structure CHAPTER 4 ATM CELL PROCESSOR Figure 4-9. Tx Buffer Elements - Tx buffer directory - Tx link pointer - Tx buffer descriptor - Tx packet descriptor Page -Tx link pointer -Tx buffer descriptor Figure 4-12. Rx Pool Structure CHAPTER 4 ATM CELL PROCESSOR Figure 4-13. Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/Rx Link Pointer -Rx buffer directory -Rx link pointer -Rx buffer descriptor -Rx pool descriptor -Rx pool descriptor -Rx link pointer -Rx buffer descriptor 4.6 Initialization F/W 4.7 Commands Page Page Page Page 262 4.8 Operations Figure 4-24. Work RAM Usage Work RAM (10 Kbytes) Page Page Page (3) Tx VC table Figure 4-28. Tx VC Table Fields defined by user Fields used by DMAC Page Page Page (1) Rx VC table Figure 4-32. Receive VC Table 0 Page Page Page Page Page CHAPTER 5 ETHERNET CONTROLLER 5.1 Overview Transceiver Ethernet Controller Block IBUS PD98502 5.2 Registers Page Table 5-3. Statistics Counter Register Map Page Page Page 5.2.2 En_MACC1 (MAC Configuration Register 1) 5.2.3 En_MACC2 (MAC Configuration Register 2) 5.2.4 En_IPGT (Back-to-Back IPG Register) 5.2.5 En_IPGR (Non Back-to-Back IPG Register) 5.2.6 En_CLRT (Collision Register) 5.2.7 En_LMAX (Maximum Packet Length Register) 5.2.8 En_RETX (Retry Count Register) 5.2.9 En_LSA2 (Station Address Register 2) 5.2.10 En_LSA1 (Station Address Register 1) 5.2.11 En_PTVR (Pause Timer Value Read Register) 5.2.12 En_VLTP (VLAN Type Register) 5.2.13 En_MIIC (MII Configuration Register) 5.2.14 En_MCMD (MII Command Register) 5.2.15 En_MADR (MII Address Register) 5.2.16 En_MWTD (MII Write Data Register) 5.2.17 En_MRDD (MII Read Data Register) 5.2.18 En_MIND (MII Indicate Register) 5.2.19 En_AFR (Address Filtering Register) 5.2.20 En_HT1 (Hash Table Register 1) 5.2.21 En_HT2 (Hash Table Register 2) Page Page Page 5.2.26 En_TXCR (Transmit Configuration Register) Page 5.2.28 En_TXDPR (Transmit Descriptor Pointer) 5.2.29 En_RXCR (Receive Configuration Register) Page 5.2.32 En_RXPDR (Receive Pool Descriptor Pointer) 5.2.33 En_CCR (Configuration Register) 5.2.34 En_ISR (Interrupt Serves Register) Page 300 5.3 Operation Page Page Page Page . Set RCVDP Set RXE Page Page CHAPTER 6 USB CONTROLLER 6.1 Overview SIE EPC IBUS MCONT Rx FIFO USB 6.2 Registers Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 6.2.24 U_TMSA (USB Tx MailBox Start Address Register) 6.2.25 U_TMBA (USB Tx MailBox Bottom Address Register) 6.2.26 U_TMRA (USB Tx MailBox Read Address Register) 6.2.27 U_TMWA (USB Tx MailBox Write Address Register) 6.2.28 U_RMSA (USB Rx MailBox Start Address Register) 6.2.29 U_RMBA (USB Rx MailBox Bottom Address Register) 6.2.30 U_RMRA (USB Rx MailBox Read Address Register) 6.2.31 U_RMWA (USB Rx MailBox Write Address Register) PD98502 6.4 Initialization Page Page 334 6.5 Data Transmit Function Data Segment 64 Bytes 64 Bytes 64 Bytes 64 Bytes 40 Bytes Tx Packet Buffer Directory Page Page Page Page Page Page Page Page 344 6.6 Data Receive Function Data Segment 64 Bytes 64 Bytes 64 Bytes 64 Bytes 40 Bytes Buffer Direc tory Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Buffer Dire ctory Page Page 364 6.7 Power Management Page VR4120A USB Controller Host PC PD98502 6.8 Receiving SOF Packet 368 6.9 Loopback Mode 6.10 Example of Connection PD98502 370 CHAPTER 7 PCI CONTROLLER 7.1 Overview 7.2 Bus Bridge Functions Page Page Page Page Page Page Page Page Page Page Page 7.3 PCI Power Management Interface PCI-Host PCI Contro ller Intern al Contro ller PCI-Host PCI Contr oller Internal Contr oller 386 7.4 Functions in Host-mode Page Page Page 390 7.5 Registers Page Page Page Page Page Page Page Page Page Page 7.5.19 P_CONFIG (PCI Configuration Registers) 7.5.19.1 PCI configuration register map Note The view from PCI side address is assigned by Register Memory Base Address Register. Page Page Page Page Page Page Page Page Page 7.6 Information for Software Page Page 414 CHAPTER 8 UART 8.1 Overview 8.2 UART Block Diagram URSDI URCLK 8.3 Registers Page Table 8-1. Correspondence between Baud Rates and Divisors Page Page Page Page Page Page 424 CHAPTER 9 TIMER 9.1 Overview 9.2 Block Diagram 9.3 Registers Page CHAPTER 10 MICRO WIRE 10.1 Overview 428 10.2 Operations 10.3 Registers 10.3.1 Register map 10.3.2 ECCR (EEPROM Command Control Register) 10.3.3 ERDR (EEPROM Read Data Register) 10.3.4 MACAR1 (MAC Address Register 1) 10.3.6 MACAR3 (MAC Address Register 3) APPENDIX A MIPS III INSTRUCTION SET DETAILS A.1 Instruction Notation Conventions Table A-1. CPU Instruction Operation Notations A.2 Load and Store Instructions 434 A.3 Jump and Branch Instructions Page ADD Add ADD ADDI Add Immediate ADDI ADDI 0 0 1 0 0 0 rt immediate 438 ADDIU g ned ADDIU ADDIU 0 0 1 0 0 1 rt immediate ADDU Add Unsigned ADDU rs 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd 0 ADDU 1 0 0 0 0 1 AND And AND ANDI And Immediate ANDI ANDI 0 0 1 1 0 0 rt immediate 442 BC0F Branch On Coprocessor 0 False BC0F 0 0 0 0 0 offset 0 1 0 0 X X BC0FL p rocessor 0 False Likel 0 0 0 1 0 offset y BC0FL p rocessor 0 False Likel y BC0T Branch On Coprocessor 0 True BC0T 0 0 0 0 1 offset 0 1 0 0 X X 446 BC0TL Branch On Coprocessor 0 True Likely (1/2) BC0TL 0 1 0 0 X X BCTL 0 0 0 1 1 offset BC0TL Branch On Coprocessor 0 True Likely (2/2) BC0TL Opcode Table: BEQ Branch On Equal BEQ BEQ 0 0 0 1 0 0 rt offset BEQL Branch On Equal Likely BEQL BEQL 0 1 0 1 0 0 rt offset BGEZ Branch On Greater Than Or Equal To Zero BGEZ BGEZ 0 0 0 0 1 offset BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL BGEZAL 1 0 0 0 1 offset BGEZALL Branch On Greater Than Or Equal To Zero And Link Likely BGEZALL BGEZALL 1 0 0 1 1 offset BGEZL Branch On Greater Than Or Equal To Zero Likely BGEZL BGEZL 0 0 0 1 1 offset BGTZ Branch On Greater Than Zero BGTZ BGTZ 0 0 0 1 1 1 BGTZL Branch On Greater Than Zero Likely BGTZL BGTZL 0 1 0 1 1 1 BLEZ Branch On Less Than Or Equal To Zero BLEZ BLEZ BLEZL Branch On Less Than Or Equal To Zero Likely BLEZL BLEZL 0 1 0 1 1 0 BLTZ Branch On Less Than Zero BLTZ BLTZ BLTZAL Branch On Less Than Zero And Link BLTZAL BLTZAL 1 0 0 0 0 offset 460 BLTZALL Branch On Less Than Zero And Link Likely BLTZALL REGIMM 0 0 0 0 0 1 BLTZALL 1 0 0 1 0 offset BLTZL Branch On Less Than Zero Likely BLTZL BLTZL 0 0 0 1 0 offset BNE Branch On Not Equal BNE BNE 0 0 0 1 0 1 rt offset BNEL Branch On Not Equal Likely BNEL BNEL 0 1 0 1 0 1 rt offset BREAK Breakpoint BREAK CACHE Cache (1/4) CACHE CACHE 1 0 1 1 1 1 op offset CE CACHE Cache (2/4) CACHE CACHE Cache (3/4) CACHE CACHE Cache (4/4) CACHE DADD Doubleword Add DADD DADD 1 0 1 1 0 0 DADDI Doubleword Add Immediate DADDI DADDI 0 1 1 0 0 0 rt immediate DADDIU Doubleword Add Immediate Unsigned DADDIU DADDIU 0 1 1 0 0 1 rt immediate DADDU Doubleword Add Unsigned DADDU DDIV Doubleword Divide DDIV DDIV 0 1 1 1 1 0 474 DDIVU Doubleword Divide Unsigned DDIVU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rt 0 DDIVU 0 1 1 1 1 1 DIV Divide DIV DIV 0 1 1 0 1 0 476 DIVU Divide Unsigned DIVU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rt 0 DIVU 0 1 1 0 1 1 DMACC Doubleword Multiply and Accumulate (1/3) DMACC 0 0 0 0 0 0 rt 1 DMACC 1 0 1 0 0 1 rd sat us0 0 0 DMACC Doubleword Multiply and Accumulate (2/3) DMACC DMACC Doubleword Multiply and Accumulate (3/3) DMACC DMFC0 DMTC0 Doubleword Move To System Control Coprocessor DMTC0 DMT 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 rt rd DMULT Doubleword Multiply DMULT DMULT 0 1 1 1 0 0 DMULTU Doubleword Multiply Unsigned DMULTU DMULTU 0 1 1 1 0 1 DSLL Doubleword Shift Left Logical DSLL 1 1 1 0 0 0 0 0 0 0 0 0 rt rd sa DSLL DSLLV Doubleword Shift Left Logical Va riable DSLLV DSLL32 Doubleword Shift Left Logical + 32 DSLL32 1 1 1 1 0 0 0 0 0 0 0 0 rt rd sa DSLL32 DSRA Doubleword Shift Right Arithmetic DSRA 1 1 1 0 1 1 0 0 0 0 0 0 rt rd sa DSRA DSRAV Doubleword Shift Right Arithmetic Variable DSRAV DSRAV 0 1 0 1 1 1 DSRA32 Doubleword Shift Right Arithmetic + 32 DSRA32 1 1 1 1 1 1 0 0 0 0 0 0 rt rd sa DSRA32 DSRL Doubleword Shift Right Logical DSRL 1 1 1 0 1 0 0 0 0 0 0 0 rt rd sa DSRL DSRLV Doubleword Shift Right Logical V ariable DSRLV DSRL32 Doubleword Shift Right Logical + 32 DSRL32 1 1 1 1 1 0 0 0 0 0 0 0 rt rd sa DSRL32 DSUB Doubleword Subtract DSUB DSUBU Doubleword Subtract Unsigned DSUBU ERET Exception Return ERET ERET 0 1 1 0 0 0 SR1 EXL ERL HIBERNATE Hibernate HIBERNATE JJump J J 0 0 0 0 1 0 target JAL Jump And Link JAL JAL 0 0 0 0 1 1 target JALR Jump And Link Register JALR 0 0 0 0 0 0 not rd rs JALX Jump And Link Exchange JALX JALX 011101 target JR Jump Register JR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JR 0 0 1 0 0 0 LB Load Byte LB LB 1 0 0 0 0 0 rt offset LBU Load Byte Unsigned LBU LBU 1 0 0 1 0 0 rt offset LD Load Doubleword LD LD 1 1 0 1 1 1 rt offset LDL Load Doubleword Left (1/3) LDL LDL 0 1 1 0 1 0 rt offset LDL $24, 12 ($0) base offset LDL Load Doubleword Left (2/3) LDL LDL Load Doubleword Left (3/3) LDL LDL 508 LDR Load Doubleword Right (1/3) LDR LDR $24, 5 ($0) LDR 0 1 1 0 1 1 rt offset LDR Load Doubleword Right (2/3) LDR LDR Load Doubleword Right (3/3) LDR LDR LH Load Halfword LH LH 1 0 0 0 0 1 rt offset LHU Load Halfword Unsigned LHU LHU 1 0 0 1 0 1 rt offset LUI Load Upper Immediate LUI LUI 0 0 1 1 1 1 rt immediate LW Load Word LW LW 1 0 0 0 1 1 rt offset LWL Load Word Left (1/3) LWL LWL 1 0 0 0 1 0 rt offset LWL $24, 4 ($0) LWL Load Word Left (2/3) LWL LWL Load Word Left (3/3) LWL LWL S 518 LWR Load Word Right (1/3) LWR LWR $24, 1 ($0) LWR 1 0 0 1 1 0 rt offset LWR Load Word Right (2/3) LWR LWR Load Word Right (3/3) LWR LWR S LWU Load Word Unsigned LWU LWU 1 0 1 1 1 1 rt offset 522 MACC Multiply and Accumulate (1/5) MACC 0 0 0 0 0 0 rt 1 MACC 1 0 1 0 0 0 rd sat us0 0 hi MACC Multiply and Accumulate (2/5) MACC MACC Multiply and Accumulate (3/5) MACC MACC Multiply and Accumulate (4/5) MACC MACC Multiply and Accumulate (5/5) MACC MFC0 Move From System Control Coprocessor MFC0 MFHI Move From HI MFHI MFLO Move From LO MFLO MTC0 Move To Coprocessor0 MTC0 MTHI MTHI MTLO Move To LO MTLO MULT Multiply MULT MULT 0 1 1 0 0 0 rt MULTU Multiply Unsigned MULTU MULTU 0 1 1 0 0 1 rt NOR Nor NOR OR Or OR ORI Or Immediate ORI ORI 0 0 1 1 0 1 rt immediate SB Store Byte SB SB 1 0 1 0 0 0 rt offset SD Store Doubleword SD SD 1 1 1 1 1 1 rt offset 540 SDL Store Doubleword Left (1/3) SDL SDL 1 0 1 1 0 0 rt offset SDL $24, 8 ($0) SDL Store Doubleword Left (2/3) SDL SDL Store Doubleword Left (3/3) SDL SDL SDR Store Doubleword Right (1/3) SDR SDR 1 0 1 1 0 1 rt offset SDR $24, 1 ($0) SDR Store Doubleword Right (2/3) SDR SDR Store Doubleword Right (3/3) SDR SDR SH Store Halfword SH SH 1 0 1 0 0 1 rt offset SLL Shift Left Logical SLL 0 0 0 0 0 0 0 0 0 0 0 0 rt rd sa SLL 0 548 SLLV Shift Left Logical Variable SLLV 0 0 0 0 0 0 rt rd 0 SLLV 0 0 0 1 0 0 SLT Set On Less Than SLT SLT 1 0 1 0 1 0 SLTI Set On Less Than Immediate SLTI SLTI 0 0 1 0 1 0 rt immediate SLTIU Set On Less Than Immediate Unsigned SLTIU SLTIU 0 0 1 0 1 1 rt immediate SLTU Set On Less Than Unsigned SLTU SLTU 1 0 1 0 1 1 SRA Shift Right Arithmetic SRA 0 0 0 0 1 1 0 0 0 0 0 0 rt rd sa SRA 554 SRAV Shift Right Arithmetic Variable SRAV SRAV 0 0 0 1 1 1 SRL Shift Right Logical SRL 0 0 0 0 1 0 0 0 0 0 0 0 rt rd sa SRL SRLV Shift Right Logical Variable SRLV SRLV rs, rt STANDBY Standby STANDBY SUB Subtract SUB SUB 1 0 0 0 1 0 SUBU Subtract Unsigned SUBU SUBU 1 0 0 0 1 1 SUSPEND Suspend SUSPEND SW Store Word SW SW 1 0 1 0 1 1 rt offset 562 SWL Store Word Left (1/3) SWL SWL $24, 4 ($0) SWL 1 0 1 0 1 0 rt offset SWL Store Word Left (2/3) SWL SWL Store Word Left (3/3) SWL SWL SWR Store Word Right (1/3) SWR SWR 1 0 1 1 1 0 rt offset SWR $24, 1 ($0) SWR Store Word Right (2/3) SWR SWR Store Word Right (3/3) SWR SWR SYNC Synchronize SYNC SYSCALL System Call SYSCALL 570 TEQ Trap If Equal TEQ TEQ 1 1 0 1 0 0 TEQI Trap If Equal Immediate TEQI TEQI 0 1 1 0 0 immediate 32 T: if GPR [rs] = (immediate15)16 || immediate15...0 then 64 T: if GPR [rs] = (immediate15)48 || immediate15...0 then TGE Trap If Greater Than Or Equal TGE TGE 1 1 0 0 0 0 TGEI Trap If Greater Than Or Equal Immediat e TGEI TGEI 0 1 0 0 0 immediate 32 T: if GPR [rs] > (immediate15)16 || immediate15...0 then 64 T: if GPR [rs] > (immediate15)48 || immediate15...0 then TGEIU TGEIU 0 1 0 0 1 immediate 32 T: if (0 || GPR [rs]) > (0 || (immediate15)16 || immediate15...0) then 64 T: if (0 || GPR [rs]) > (0 || (immediate15)48 || immediate15...0) then TGEU Trap If Greater Than Or Equal Unsigned TGEU TGEU 1 1 0 0 0 1 TLBP Probe TLB For Matching Entry TLBP TLBP 0 0 1 0 0 0 TLBR Read Indexed TLB Entry TLBR TLBR TLBWI Write Indexed TLB Entry TLBWI TLBWI 0 0 0 0 1 0 TLBWR Write Random TLB Entry TLBWR TLBWR TLT Trap If Less Than TLT TLT 1 1 0 0 1 0 TLTI Trap If Less Than Immediate TLTI TLTI 0 1 0 1 0 immediate 32 T: if GPR [rs] < (immediate15)16 || immediate15...0 then 64 T: if GPR [rs] < (immediate15)48 || immediate15...0 then TLTIU Trap If Less Than Immediate Unsigned TLTIU TLTIU 0 1 0 1 1 immediate 32 T: if (0 || GPR [rs]) < (0 || (immediate15)16 || immediate15...0) then 64 T: if (0 || GPR [rs]) < (0 || (immediate15)48 || immediate15...0) then TLTU Trap If Less Than Unsigned TLTU TLTU 1 1 0 0 1 1 584 TNE Trap If Not Equal TNE TNE 1 1 0 1 1 0 TNEI Trap If Not Equal Immediate TNEI TNEI 0 1 1 1 0 immediate 32 T: if GPR [rs] (imm ediate15)16 || immediate15...0 then 64 T: if GPR [rs] (imm ediate15)48 || immediate15...0 then XOR Exclusive Or XOR XORI Exclusive OR Immediate XORI XORI 0 0 1 1 1 0 rt immediate 588 A.6 CPU Instruction Opcode Bit Encoding Figure A-1 lists the VR4120A Opcode Bit Encoding. Figure A-1. V Page 590 APPENDIX B VR4120A COPROCESSOR 0 HAZARDS Table B-1. VR4120A CPU Coprocessor 0 Hazards Page Page Page Facsimile Message Thank you for your kind support. From: