NEC uPD98502 - page 420

CHAPTER 8 UART
420 Preliminary User’s Manual S15543EJ1V0UM
8.3.9 UARTLCR (UART Line Control Register)
This register is used to specify the format for asynchronous communication and exchange and to set the divisor
latch access bit. Bit 6 is used to send the break status to the receive side’s UART. When bit 6 = 1, the serial output
(URSDO) is forcibly set to the spacing (0) state. The setting of bit 5 becomes valid according to settings in bits 4 and
3.
Bits Field R/W Default Description
31:8 Reserved R/W 0 Hardwired to 0.
7 DLAB R/W 0 Divisor Latch access bit.
1 = access baud-rate divisor at offset 84H
0 = access URSDO/URSDI and IE at offset 84H
When this bit is set, UART accesses the UART Divisor Latch LSB Register
(UARTDLM) at offset 84H. When cleared, the UART accesses the Receiver
Data Buffer Register (UARTRBR) on reads at offset 80H, the UARTTHR on
writes at offset 80H, and UARTIER on any accesses at offset 84H.
6 USB R/W 0 Send Break
1 = force URSDO signal output Low
0 = normal operation
5 USP R/W 0 Stick parity.
1 = force URSDO signal output Low
0 = normal operation
4 EPS R/W 0 Parity se lect.
1 = even parity
0 = odd parity
3 PEN R/W 0 Parity enable.
1 = generate parity on writes, check it on reads.
0 = no parity generation or checking.
For the UART, even or odd parity can be generated or checked, as specified
in Bit 4 (EPS).
2 STB R/W 0 Number of stop bits.
1 = 2 bits, except 1.5 stop bits for 5bits / words (WLS = 00)
0 = 1 bit
1:0 WLS R/W 00 Word length select.
11 = 8 bits
10 = 7 bits
01 = 6 bits
00 = 5 bits