Preliminary User’s Manual S15543EJ1V0UM 11
4.4.18 A_T1R (T1 Time Register)...........................................................................................................245
4.4.19 A_TSR (Time Stamp Register)....................................................................................................245
4.4.20 A_IBBAR (IBUS Base Address Register)....................................................................................245
4.4.21 A_INBAR (Instruction Base Address Register)............................................................................245
4.4.22 A_UMCMD (UTOPIA Management Interface Command Register).............................................246
4.5 Data Structure.......................................................................................................................... 247
4.5.1 Tx buffer structure....................................................................................................................... 247
4.5.2 Rx pool structure......................................................................................................................... 250
4.6 Initialization.............................................................................................................................. 255
4.6.1 Before starting RISC core............................................................................................................255
4.6.2 After RISC core’s F/W is starting.................................................................................................256
4.7 Commands ...............................................................................................................................257
4.7.1 Set_Link_Rate command............................................................................................................258
4.7.2 Open_Channel command............................................................................................................258
4.7.3 Close_Channel command...........................................................................................................259
4.7.4 Tx_Ready command....................................................................................................................260
4.7.5 Add_Buffers command................................................................................................................261
4.7.6 Indirect_Access command...........................................................................................................262
4.8 Operations................................................................................................................................ 262
4.8.1 Work RAM usage........................................................................................................................ 262
4.8.2 Transmission function..................................................................................................................263
4.8.3 Receiving function.......................................................................................................................270
4.8.4 Mailbox........................................................................................................................................276
CHAPTER 5 ETHERNET CONTROLLER..........................................................................................2775.1 Overview................................................................................................................................... 277
5.1.1 Features...................................................................................................................................... 277
5.1.2 Block diagram of Ethernet controller block..................................................................................277
5.2 Registers...................................................................................................................................279
5.2.1 Register map...............................................................................................................................279
5.2.2 En_MACC1 (MAC Configuration Register 1)...............................................................................285
5.2.3 En_MACC2 (MAC Configuration Register 2)...............................................................................286
5.2.4 En_IPGT (Back-to-Back IPG Register)........................................................................................286
5.2.5 En_IPGR (Non Back-to-Back IPG Register)................................................................................286
5.2.6 En_CLRT (Collision Register)......................................................................................................287
5.2.7 En_LMAX (Maximum Packet Length Register)...........................................................................287
5.2.8 En_RETX (Retry Count Register)................................................................................................287
5.2.9 En_LSA2 (Station Address Register 2)........................................................................................287
5.2.10 En_LSA1 (Station Address Register 1)........................................................................................287
5.2.11 En_PTVR (Pause Timer Value Read Register)...........................................................................288
5.2.12 En_VLTP (VLAN Type Register).................................................................................................288
5.2.13 En_MIIC (MII Configuration Register)..........................................................................................288
5.2.14 En_MCMD (MII Command Register)...........................................................................................288
5.2.15 En_MADR (MII Address Register)...............................................................................................289
5.2.16 En_MWTD (MII Write Data Register)...........................................................................................289
5.2.17 En_MRDD (MII Read Data Register)...........................................................................................289
5.2.18 En_MIND (MII Indicate Register).................................................................................................289
5.2.19 En_AFR (Address Filtering Register)...........................................................................................290