CHAPTER 6 USB CONTROLLER
316 Preliminary User’s Manual S15543EJ1V0UM
6.2.5 U_IMR1 (USB Interrupt Mask Register 1)This register is used to mask interrupts.When a bit in this register is set to a ‘1’ and the corresponding bit in the USB General Status Register 1 (Address:10H) is set to a ‘1’, an interrupt is issued.
Bits Field R/W Default Description
31 GSR2 R/W 0 General Status Register 2 Interrupt:
1 = unmask.
0 = mask.
30:24 Reserved R/W 0 Reserved for future use. Writes ‘0’s.
23 TMF R/W 0 Tx MailBox Full:
1 = unmask.
0 = mask.
22 RMF R/W 0 Rx MailBox Full:
1 = unmask.
0 = mask.
21 RPE2 R/W 0 Rx Pool2 Empty:
1 = unmask.
0 = mask.
20 RPE1 R/W 0 Rx Pool1 Empty:
1 = unmask.
0 = mask.
19 RPE0 R/W 0 Rx Pool0 Empty:
1 = unmask.
0 = mask.
18 RPA2 R/W 0 Rx Pool2 Alert:
1 = unmask.
0 = mask.
17 RPA1 R/W 0 Rx Pool1 Alert:
1 = unmask.
0 = mask.
16 RPA0 R/W 0 Rx Pool0 Alert:
1 = unmask.
0 = mask.
15:11 Reserved R/W 0 Reserved for future use. Writes ‘0’s.
10 DER R/W 0 DMA Error:
1 = unmask.
0 = mask.
9 EP2FO R/W 0 EP2 FIFO Error:
1 = unmask.
0 = mask.
8 EP1FU R/W 0 EP1 FIFO Error:
1 = unmask.
0 = mask.
7 EP6RF R/W 0 EP6 Rx Finished:
1 = unmask.
0 = mask.
6 EP5TF R/W 0 EP5 Tx Finished:
1 = unmask.
0 = mask.
5 EP4RF R/W 0 EP4 Rx Finished:
1 = unmask.
0 = mask.