CHAPTER 3 SYSTEM CONTROLLER
192 Preliminary User’s Manual S15543EJ1V0UM
3.2.4 S_ISR (Interrupt Status Register)
The interrupt status register “S_ISR” is a read-clear and 32-bit word-aligned register. S_ISR indicates the
interruption status from SysAD/IBUS interfaces, timer, UART and so on. If corresponding bit in S_IMR (Interrupt Mask
Register) is set and the interrupt is not masked, system controller interrupts to VR4120A using interrupt signal. The bit
in S_ISR is reset after being read by the VR4120A. When the same type of incident occurs before the bit has been
read, the bit will be set again. S_ISR is initialized to 0 at reset and contains the following fields:
Bits Field R/W Default Description
31:18 Reserved RC 0 Hardwired to 0.
17 MAC2IS RC 0 MAC2 interrupt:
0 = no MAC2 interrupt pending.
1 = MAC2 interrupt pending.
16 PCIIS RC 0 PCI interrupt:
0 = no PCI interrupt pending.
1 = PCI interrupt pending.
15:5 Reserved RC 0 Hardwired to 0.
4 WUIS RC 0 Wakeup interrupt:
0 = no wakeup request pending.
1 = some wakeup request pending.
3 EXTIS RC 0 External interrupt:
0 = no external interrupt pending.
1 = external interrupt pending.
2 UARTIS RC 0 UART interrupt:
0 = no UART interrupt pending.
1 = UART interrupt pending.
UART interruption is one of the following interruptions:
1. UART receive data buffer full interrupt
2. UART transmitter buffer empty interrupt
3. UART line status interrupt
4. UART modem status interrupt
1 TM1IS RC 0 Timer CH1 interrupt:
0 = no timer CH1 interrupt pending.
1 = timer CH1 interrupt pending.
0 TM0IS RC 0 Timer CH0 interrupt:
0 = no timer CH0 interrupt pending.
1 = timer CH0 interrupt pending.
Remarks 1. To clear bits 0 to 4 in this register, the VR4120A must read the byte that contains the TM0IS register.
In addition, to clear bits 16 to 17, the VR4120A must read the byte that contains the PCIIS register.
2. MAC2 interrupt and PCI interrupt can not be masked by system controller.
3. After clearing MAC2IS/PCIIS bit, MAC/PCI block continues to provide interrupt signal to VR4120A.