NEC uPD98502 - page 151

CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 151
(3) TLB modified exception
(a) Cause
The TLB Modified exception occurs when the TLB entry that matches with the virtual address referenced by the
store instruction is valid (V bit is 1) but is not writeable (D bit is 0). This exception is not maskable.
(b) Processing
The common exception vector is used for this exception, and the Mod code in the ExcCode field of the Cause
register is set.
When this exception occurs, the BadVAddr, Context, Xcontext, and EntryHi registers contain the virtual address
that failed address translation. The EntryHi register also contains the ASID from which the translation fault
occurred. The contents of the EntryLo register are undefined.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(c) Servicing
The kernel uses the failed virtual address or virtual page number to identify the corresponding access control bits.
The page identified may or may not permit write accesses; if writes are not permitted, a write protection violation
occurs.
If write accesses are permitted, the page frame is marked dirty (/writeable) by the kernel in its own data structures.
The TLBP instruction places the index of the TLB entry that must be altered into the Index register. The word data
containing the physical page frame and access control bits (with the D bit set to 1) is loaded to the EntryLo
register, and the contents of the EntryHi and EntryLo registers are written into the TLB.