CHAPTER 2 VR4120A
Preliminary User’s Manual S15543EJ1V0UM 127
Figure 2-46. TLB Address Translation
Virtual address (input)
VPN
and
ASID
Exception Exception
ExceptionException
Ph
y
sical Address
(
output
)
Exception
No
Yes
Yes
YesNo
Yes
YesNo
Address
OK?
Supervisor
mode?
User
mode?
Address
OK?
Address
OK?
No
No
Yes
Yes
Yes
Mapped
address?
No
VPN
match?
Dirty
Valid
Global
No
G = 1?
No
V = 1?
Yes
Yes
No
D = 1?
No
Yes
Uncached
area?
No
ASID
match?
No
32-bit
address?
Yes
Yes
TLB
Mismatch
TLB
Invalid
No
No
Yes
Write?
Access
main memory
Access
cache memory
Exception
Address
error
Address
error
Address
error
Exception
TLB
Modified XTLB
Mismatch
2.4.5.12 TLB missesIf there is no TLB entry that matches the virtual address, a TLB Refill (miss) exception occursNote. If the accesscontrol bits (D and V) indicate that the access is not valid, a TLB Modified or TLB Invalid exception occurs. If the C bitis 010, the retrieved physical address directly accesses main memory, bypassing the cache.Note See Section 2.5 Exception Processing for details of the TLB Miss exception.